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| nxp semiconductors data sheet: technical data document number: IMX6ULLIEC rev. 1.2, 11/2017 ordering information see table 1 on page 3 mcimx6y0cvm05aa mcimx6y0cvm05ab mcimx6y1cvm05aa mcimx6y1cvm05ab mcimx6y1cvk05aa mcimx6y1cvk05ab mcimx6y2cvm05aa mcimx6y2cvm05ab mcimx6y2cvm08aa mcimx6y2cvm08ab mcimx6y2cvk08ab package information plastic package mapbga 14 x 14 mm, 0.8 mm pitch mapbga 9 x 9 mm, 0.5 mm pitch ? 2016-2017 nxp b.v. 1 i.mx 6ull introduction the i.mx 6ull processors represent nxp?s latest achievement in integrated multimedia-focused products offering high performance proc essing with a high degree of functional integration, ta rgeted towards the growing market of connected devices. the i.mx 6ull is a high performance, ultra efficient processor family with featuring nxp?s advanced implementation of the single arm cortex ? -a7 core, which operates at speeds of up to 792 mhz. i.mx 6ull includes integrated power management module that reduces the complexity of external power supply and simplifies the power sequencin g. each processor in this family provides various memory interfaces, including lpddr2, ddr3, ddr3l, raw and managed nand flash, nor flash, emmc, quad spi, and a wide range of other interfaces for connecti ng peripherals, such as wlan, bluetooth?, gps, displays, and camera sensors. i.mx 6ull applications processors for industrial products 1. i.mx 6ull introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1. ordering information . . . . . . . . . . . . . . . . . . . . . . . 3 1.2. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1. special signal considerations . . . . . . . . . . . . . . . 18 3.2. recommended connections for unused analog interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21 4.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . 21 4.2. power supplies requirements and restrictions . 31 4.3. integrated ldo voltage regulator parameters . . 32 4.4. pll?s electrical characteristics . . . . . . . . . . . . . . . 34 4.5. on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . 36 4.6. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . 37 4.7. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . 40 4.8. output buffer impedance parameters . . . . . . . . . 43 4.9. system modules timing . . . . . . . . . . . . . . . . . . . . 46 4.10. multi-mode ddr controller (mmdc) . . . . . . . . . . 57 4.11. general-purpose media interface (gpmi) timing 58 4.12. external peripheral interface parameters . . . . . . . 66 4.13. a/d converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 5. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . 103 5.1. boot mode configuration pins . . . . . . . . . . . . . . 103 5.2. boot device interface allocation . . . . . . . . . . . . . 104 6. package information and contact assignments . . . . . 111 6.1. 14 x 14 mm package information . . . . . . . . . . . . 111 6.2. 9 x 9 mm package information . . . . . . . . . . . . . . 124 7. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 2 nxp semiconductors i.mx 6ull introduction the i.mx 6ull processors are specifically useful fo r applications such as: ? telematics ? audio playback ? connected devices ? iot gateway ? access control panels ? human machine interfaces (hmi) ? portable medical and health care ? ip phones ? smart appliances ?ereaders the features of the i.mx 6ull processors include: ? single-core arm cortex -a7?the single core a7 provides a cost-effective and power-efficient solution. ? multilevel memory system?the multilevel memo ry system of processor is based on the l1 instruction and data caches, l2 cache, and intern al and external memory. the processor supports many types of external memory devices, in cluding ddr3, low voltage ddr3, lpddr2, nor flash, nand flash (mlc and slc), onenand ?, quad spi, and managed nand, including emmc up to rev 4.4/4.41/4.5. ? smart speed technology?power management implemented throughout the ic that enables multimedia features and peripherals to consum e minimum power in both active and various low power modes. ? dynamic voltage and frequency sc aling?the power efficiency of devices by scaling the voltage and frequency to optimize performance. ? multimedia powerhouse?the multimedia performance of proces sor is enhanced by a multilevel cache system, neon? mpe (media processor engine) co-processor, a programmable smart dma (sdma) controller, an asynchronous audio sample rate converter, an electrophoretic display (epd) controller, and a pixel processing pipe line (pxp) to support 2d image processing, including color-space conversion, scaling, alpha-blending, and rotation. ? 2x ethernet interfaces?2x 10/100 mbps ethernet controllers. ? human-machine interface?each processor suppor ts one digital parallel display interface. ? interface flexibility?each processor supports connections to a variet y of interfaces: two high-speed usb on-the-go with phy, multiple e xpansion card ports (high-speed mmc/sdio host and other), two 12-bit adc modules with up to 10 total input channels and two can ports. ? advanced security?the processors deliver hardware -enabled security featur es that enable secure e-commerce, digital rights mana gement (drm), information encryption, secure boot, aes-128 encryption, sha-1, sha-256 hw acc eleration engine, and secure software downloads. the security features are discussed in the i.mx 6ull security reference manual (imx6ullsrm). i.mx 6ull introduction i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 3 ? integrated power management?the processors integrate linear regul ators and internally generate voltage levels for different domains. this si gnificantly simplifies system power management structure. for a comprehensive list of the i.mx 6ull features, see section 1.2, ?features " ? . 1.1 ordering information table 1 provides examples of or derable part numbers cove red by this data sheet. table 1. ordering information part number feature package junction temperature t j ( ? c) mcimx6y0cvm05aa mcimx6y0cvm05ab features supports: ? 528 mhz, industrial grade for general purpose ? no security ? no lcd/csi ?no can ? ethernet x1 ? usb otg x1 ? adc x1 ?uart x4 ?sai x1 ? no esai ?timer x2 ?pwm x4 ?i2c x2 ?spi x2 14 x 14 mm, 0.8 pitch mapbga -40 to +105 mcimx6y1cvm05aa mcimx6y1cvm05ab features supports: ? 528 mhz, industrial grade for general purpose ? basic security ? no lcd/csi ?can x1 ? ethernet x1 ? usb otg x2 ? adc x1 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 14 x 14 mm, 0.8 pitch mapbga -40 to +105 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 4 nxp semiconductors i.mx 6ull introduction mcimx6y1cvk05aa mcimx6y1cvk05ab features supports: ? 528 mhz, industrial grade for general purpose ? basic security ? no lcd/csi ?can x1 ? ethernet x1 ? usb otg x2 ? adc x1 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 9 x 9 mm, 0.5 pitch mapbga -40 to +105 mcimx6y2cvm05aa mcimx6y2cvm05ab features supports: ? 528 mhz, industrial grade for general purpose ? basic security ? with lcd/csi ?can x2 ? ethernet x2 ? usb otg x2 ? adc x2 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 14 x 14mm, 0.8 pitch mapbga -40 to +105 table 1. ordering information part number feature package junction temperature t j ( ? c) i.mx 6ull introduction i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 5 figure 1 describes the part number nomencl ature so that the users can identify the characteristics of the specific part number they have (for example, cores, frequency, temp erature grade, fuse options, and silicon revision). the primary characteristic which describes which data sheet a pplies to a specific part is the temperature grade (junction) field. ? the i.mx 6ull applications processors for industrial pr oducts data sheet (IMX6ULLIEC) covers parts listed with a ?c (industrial temp)? ensure to have the proper data sheet for specific pa rt by verifying the temperat ure grade (junction) field and matching it to the proper data sheet. if th ere will be any questions, visit the web page nxp.com/imx6series or contact a nxp representative for details. mcimx6y2cvm08aa mcimx6y2cvm08ab features supports: ? 792 mhz, industrial grade for general purpose ? basic security ? with lcd/csi ?can x2 ? ethernet x2 ? usb otg x2 ? adc x2 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 14 x 14 mm, 0.8 pitch mapbga -40 to +105 mcimx6y2cvk08ab features supports: ? 792 mhz, industrial grade for general purpose ? basic security ? with lcd/csi ?can x2 ? ethernet x2 ? usb otg x2 ? adc x2 ?uart x8 ?sai x3 ?esai x1 ?timer x4 ?pwm x8 ?i2c x4 ?spi x4 9 x 9 mm, 0.5 pitch mapbga -40 to +105 table 1. ordering information part number feature package junction temperature t j ( ? c) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 6 nxp semiconductors i.mx 6ull introduction figure 1. part number nomenclature?i.mx 6ull 1.2 features the i.mx 6ull processors are based on arm cortex-a7 mpcore? pl atform, which has the following features: ? supports single arm cortex-a7 mp core (with trustzone) with: ? 32 kb l1 instruction cache ? 32 kb l1 data cache ? private timer and watchdog ? cortex-a7 neon media processing engine (mpe) co-processor ? general interrupt controller (gic) with 128 interrupts support ? global timer ? snoop control unit (scu) ? 128 kb unified i/d l2 cache ? single master axi bus interface output of l2 cache part differentiator @ with epdc 7 reserved 6 5 4 3 general purpose 2 (full feature) 2 general purpose 1 (reduced feature) 1 baseline 0 junction temperature (tj) + consumer: 0 to + 95 c d industrial: -40 to +105 c c arm cortex-a7 frequency $$ 528 mhz 05 792 mhz 08 900 mhz 09 package type rohs mapbga 14 x 14 mm, 0.8 pitch vm mapbga 9 x 9 mm, 0.5 pitch vk qualification level mc prototype samples pc mass production mc special sc i.mx 6 family x i.mx 6ull y silicon rev a rev 1.0 (mask number: 0n70s) a rev 1.1 (mask number: 1n70s) b fuse option % reserved a mc imx6 x @ + vv $$ % a i.mx 6ull introduction i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 7 ? frequency of the core (includi ng neon and l1 cache), as per table 10, "operating ranges," on page 24 . ? neon mpe coprocessor ? simd media processing architecture ? neon register file with 32x64- bit general-purpose registers ? neon integer execute pipe line (alu, shift, mac) ? neon dual, single-precision floating poi nt execute pipeli ne (fadd, fmul) ? neon load/store and permute pipeline ? 32 double-precision vfpv3 floating point registers the soc-level memory system consists of the following a dditional components: ? boot rom, including hab (96 kb) ? internal multimedia/shared, fa st access ram (ocram, 128 kb) ? external memory interfaces: the i.mx 6ull proces sors support latest, high volume, cost effective handheld dram, nor, and nan d flash memory standards. ? 16-bit lp-ddr2-800, 16-bit ddr3-800 and ddr3l-800 ? 8-bit nand-flash, including support for raw ml c/slc, 2 kb, 4 kb, and 8 kb page size, ba-nand, pba-nand, lba-n and, onenand? and others. bch ecc up to 40 bits. ? 16/8-bit nor flash. all eimv2 pins are muxed on other interfaces. each i.mx 6ull processor enables th e following interfaces to external devices (some of them are muxed and not available simultaneously): ?displays: ? one parallel display port, support max 85 mhz display clock and up to wxga (1366 x 768) at 60 hz ? support 24-bit, 18-bit, 16-bit, and 8-bit parallel display ? electrophoretic display contro ller support direct-d river for e-ink epd panel, with up to 2048x1536 resolution at 106 hz ? camera sensors: ? one parallel camera port, up to 24 bit and 133.3 mhz pixel clock ? support 24-bit, 16-bit, 10-bit, and 8-bit input ? support bt.656 interface ? expansion cards: ? two mmc/sd/sdio card ports all supporting: ? 1-bit or 4-bit transfer mode specifications for sd and sd io cards up to uhs-i sdr-104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specific ations for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? 4-bit or 8-bit transfer m ode specifications for emmc ch ips up to 200 mhz in hs200 mode (200 mb/s max) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 8 nxp semiconductors i.mx 6ull introduction ?usb : ? two high speed (hs) usb 2.0 otg (up to 480 mbps), with integrated hs usb phy ? miscellaneous ips and interfaces: ? three i2s/sai/ac97, up to 1.4 mbps each ?esai ? sony philips digital interface format (spdif), rx and tx ? eight uarts, up to 5.0 mbps each: ? providing rs232 interface ? supporting 9-bit rs485 multidrop mode ? support rts/cts for hardware flow control ? four ecspi (enhanced cspi), up to 52 mbps each ? four i 2 c, supports 400 kbps ? two 10/100 ethernet controller (ieee1588 compliant) ? eight pulse width modulators (pwm) ? system jtag controller (sjc) ? gpio with interrupt capabilities ? 8x8 key pad port (kpp) ? one quad spi to connect to serial nor flash ? two flexible controller area network (flexcan) ? three watchdog timers (wdog) ? 8-bit/10-bit/12-bit/16- bit camera interface ? two 12-bit analog to digital converters (adc ) with up to 10 input channels in total the i.mx 6ull processors in tegrate advanced power mana gement unit and controllers: ? provide pmu, including ldo su pplies, for on-chip resources ? use temperature sensor for monitoring the die temperature ? use voltage sensor for monitoring the die voltage ? support dvfs techniques for low power modes ? use sw state retention and power gating for arm and neon ? support various levels of system power modes ? use flexible clock gating control scheme the i.mx 6ull processors use dedicated hardware accelerators to meet the targeted multimedia performance. the use of hardware a ccelerators is a key factor in obtai ning high performanc e at low power consumption numbers, while having the cpu core relatively free for performing other tasks. the i.mx 6ull processors incorporat e the following hardware accelerators: ? pxp?pixel processing pipeline for image resize, rotation, overlay and csc. off loading key pixel processing operations are required to support the lcd disp lay applications. ? asrc?asynchronous sample rate converter i.mx 6ull introduction i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 9 security functions are enabled and accelerated by the following hardware: ? arm trustzone including the tz architecture (s eparation of interrupts, memory mapping, etc.) ? sjc?system jtag controller. protecting jt ag from debug port attacks by regulating or blocking the access to th e system debug features. ? snvs?secure non-volatile storage, including se cure real time clock, both active tamper and passive tamper detection logic has up to 10 tamper inputs. voltage monitor, temperature monitor, and clock frequency monitor prot ects the secure key storage. ? csu?central security unit. enhancement for the ic identification module (iim). will be configured during boot and by efus es and will determine the secu rity level operation mode as well as the tz policy. ? a-hab?advanced high assurance boot?hab v4 with the new embedded enhancements: aes-128 encryption, sha-1, and sha-256 hw accel eration engine, 2048-bi t rsa key, version control mechanism, warm boot, csu, and tz initialization. note the actual feature set depends on th e part numbers as described in table 1. functions, such as display and camer a interfaces, connectivity interfaces. i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 10 nxp semiconductors architectural overview 2 architectural overview the following subsections provide an architectural overview of th e i.mx 6ull processor system. 2.1 block diagram figure 2 shows the functional modules in the i.mx 6ull processor system. . figure 2. i.mx 6ull system block diagram ' h e x j ' $ 3 7 3 , 8 & 7 , v 6 - & 6 3 % $ & o r f n 5 h v h w 3 / / & & 0 * 3 & 6 5 & ; 7 $ / 2 6 & . 2 6 & 7 l p h u & r q w u r o : ' 2 * * 3 7 ( 3 , 7 7 h p s 0 r q l w r u , p d j h 3 u r f v v l q j 3 l [ h o 3 u r f h v v l q j 3 l s h o l q h 3 ; 3 6 h f x u l w \ & 6 8 ) x v h % r [ 6 1 9 6 6 5 7 & 3 r z h u 0 d q d j h p h q w / ' 2 v : / $ 1 0 r g h p , & ' l j l w d o $ x g l r & 0 2 6 6 h q v r u / & ' 3 d q h o 7 d p s h u ' h w h f w l r q 1 2 5 ) / $ 6 + 4 x d g 6 3 , 1 2 5 ) / $ 6 + 3 d u d o o h o 8 6 % 2 7 * g h y k r v w / 3 ' ' 5 ' ' 5 . h \ s d g 0 ( w k h u q h w [ & r q w u r o o h u $ u h d 1 h w z r u n - 7 $ * , ( ( ( h , 1 . 3 d q h o 6 h q v r u v % d w w h u \ & r q w u r o ' h y l f h 0 0 & 6 ' 6 ' ; & 0 0 & 6 ' h 0 0 & h 6 ' & u \ v w d o d q g & o r f n 6 r x u f h 1 $ 1 ' ) / $ 6 + ' l v s o d \ , q w h u i d f h / & ' , ) 6 p d u w ' 0 $ 6 ' 0 $ & $ 1 [ ( [ w h u q d o 0 h p r u \ 0 0 ' & ( , 0 * 3 0 , % & + 4 6 3 , , q w h u q d o 0 h p r u \ 2 & 5 $ 0 . % 5 2 0 . % $ 5 0 & r u w h [ $ 0 3 & r u h 3 o d w i r u p & r u w h [ $ & r u h , f d k f h . % ' f d f k h . % 1 ( 2 1 ( 7 0 6 & 8 7 l p h u / & d f k h . % 6 k d u h g 3 h u l s k h u d o v h & 6 3 , 6 3 ' , ) 7 [ 5 [ 6 $ , 8 $ 5 7 $ 3 3 h u l s k h u d o v x 6 ' + & , & 3 : 0 2 & 2 7 3 , 2 0 8 ; & . 3 3 * 3 , 2 ( w k h u q h w 8 6 % 2 7 * & $ 1 & d p h u d , q w h u i d f h & 6 , $ ; , d q g $ + % 6 z l w f k ) d e u l f $ 6 5 & 0 4 6 ( 6 $ , ( o h w u r s k r u h w l f ' l v s o d \ ( 3 ' + $ % modules list i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 11 3 modules list the i.mx 6ull processors contain a variety of digital and analog modules. table 2 describes these modules in alphabetical order. table 2. i.mx 6ull modules list block mnemonic block name su bsystem brief description adc1 adc2 analog to digital converter ? the adc is a 12-bit general purpose analog to digital converter. arm arm platform arm the arm core platform includes 1x cortex-a7 core. it also includes associated sub-blocks, such as the level 2 cache controller, scu (snoop control unit), gic (general interrupt controller), private timers, watchdog, and coresight debug modules. asrc asynchronous sample rate converter multimedia peripherals the asynchronous sample rate converter (asrc) converts the sampling rate of a signal associated to an input clock into a signal associated to a different output clock. the asrc supports concurrent sample rate conversion of up to 10 channels of about -120db thd+n. the sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates. the asrc supports up to three sampling rate pairs. bch binary-bch ecc processor system control peripherals the bch module provides up to 40-bit ecc encryption/decryption for nand flash controller (gpmi) ccm gpc src clock control module, general power controller, system reset controller clocks, resets, and power control these modules are responsible for clock and reset distribution in the system, an d also for the system power management. csi parallel csi multimedia peripherals the csi ip provides parallel csi standard camera interface port. the csi parallel data ports are up to 24 bits. it is designed to support 24-bit rgb888/yuv444, ccir656 video interface, 8-bit ycbcr, yuv or rgb, and 8-bit/10-bit/16-bit bayer data input. csu central security unit security the centra l security unit (csu) is responsible for setting comprehensive securi ty policy within the i.mx 6ull platform. dap debug access port system control peripherals the dap provides real-time access for the debugger without halting the core to: ? system memory and peripheral registers ? all debug configuration registers the dap also provides debugger access to jtag scan chains. the dap module is internal to the cortex-a7 core platform. i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 12 nxp semiconductors modules list dcp data co-processor security this module provides support for general encryption and hashing functions typically used for security functions. because its basic job is moving data from memory to memory, it also incorporates a memory-copy (memcopy) function for both debugging and as a more efficient method of copying data between memory blocks than the dma-based approach. ecspi1 ecspi2 ecspi3 ecspi4 configurable spi connectivity peripherals full-duplex enhanced synchronous serial interface, with data rate up to 52 mbit/s. it is configurable to support master/slave modes, four chip selects to support multiple peripherals. eim nor-flash /psram interface connectivity peripherals the eim nor-flash / psram provides: ? support 16-bit (in muxed io mode only) psram memories (sync and async operating modes), at slow frequency ? support 16-bit (in muxed io mode only) nor-flash memories, at slow frequency ? multiple chip selects enet1 enet2 ethernet controller connectivity peripherals the ethernet media acce ss controller (mac) is designed to support 10/100 mbit/s ethernet/ieee 802.3 networks. an external transceiver interface and transceiver function are required to complete the interface to the media. the module has dedicated hardware to support the i eee 1588 standar d. see the enet chapter of the reference manual for details. epdc electrophoretic display controller multimedia peripherals the epdc is a feature-rich, low power, and high performance direct-drive active matrix epd controller. it is specially designed to drive e-ink tm epd panels, supporting a wide variety of tft backplanes. epit1 epit2 enhanced periodic interrupt timer timer peripherals each epit is a 32-bit ?set and forget? timer that starts counting after the epit is enabled by software. it is capable of providing precise interrupts at regular intervals with minimal processor intervention. it has a 12-bit prescaler for division of input clock frequency to get the required time setting for the interrupts to occur, and counter value can be programmed on the fly. table 2. i.mx 6ull modules list (continued) block mnemonic block name su bsystem brief description modules list i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 13 esai enhanced serial audio interface connectivity peripherals the enhanced serial audio in terface (esai) provides a full-duplex serial port for serial communication with a variety of serial devices, including industry-standard codecs, spdif transceivers, and other processors. the esai consists of independent transmitter and receiver sections, each section with its own clock generator. all serial transfers are synchronized to a clock. additional synchronization signals are used to delineate the word frames. the normal mode of operation is used to transfer data at a periodic rate, one word per period. the network mode is also intended for periodic transfers; however, it supports up to 32 words (time slots) per period. this mode can be used to build time division multiplexed (tdm) networks. in contrast, the on-demand mode is intended for non-periodic transfers of data and to transfer data serially at high speed when the data becomes available. the esai has 12 pins for data and clocking connection to external devices. flexcan1 flexcan2 flexible controller area network connectivity peripherals the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the electromagnetic interference (emi) environment of a vehicle, cost-effectiveness and required bandwidth. the flexcan module is a full implementation of the can protocol specification, version 2.0 b, which supports both standard and extended message frames. gpio1 gpio2 gpio3 gpio4 gpio5 general purpose i/o modules system control peripherals used for general purpose input/output to external ics. each gpio module suppor ts 32 bits of i/o. gpmi general purpose memory interface connectivity peripherals the gpmi module supports up to 8x nand devices and 40-bit ecc encryption/decryption for nand flash controller (gpmi2). gpmi supports separate dma channels for each nand device. gpt1 gpt2 general purpose timer timer peripherals each gpt is a 32-bit ?free-running? or ?set and forget? mode timer with programmable prescaler and compare and capture register. a timer counter value can be captured using an external ev ent and can be configured to trigger a capture event on either the leading or trailing edges of an input pulse. when the timer is configured to operate in ?set and forget? mode, it is capable of providing precise interrupts at regular intervals with minimal processor intervention. the counter has output compare logic to provide the status and interrupt at comparison. this timer can be configured to run either on an external clock or on an internal clock. table 2. i.mx 6ull modules list (continued) block mnemonic block name su bsystem brief description i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 14 nxp semiconductors modules list lcdif lcd interface connectivity peripherals the lcdif is a general purpose display controller used to drive a wide range of display devices varying in size and capability. the lcdif is designed to support dumb (synchronous 24-bit parallel rgb interface) and smart (asynchronous parallel mpu interface) lcd devices. mqs medium quality sound multimedia peripherals mqs is used to generate 2-channel medium quality pwm-like audio via two standard digital gpio pins. pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 pwm7 pwm8 pulse width modulation connectivity peripherals the pulse-width modulator (pwm) has a 16-bit counter and is optimized to generate sound from stored sample audio images and it can also generate tones. it uses 16-bit resolution and a 4x16 data fifo to generate sound. pxp pixel processing pipeline display peripherals a high-performance pixel processor capable of 1 pixel/clock performance for combined operations, such as color-space conversion, alpha blending, gamma-mapping, and rotation. the pxp is enhanced with features specifically for gray scale applications. in addition, the pxp supports traditional pixel/frame processing paths for still-image and video processing applications, allowing it to interface with the integrated epd. rngb random number generator security random number generating module. qspi quad spi connectivity peripherals quad spi module acts as an interface to external serial flash devices. this module contains the following features: ? flexible sequence engine to support various flash vendor devices ? single pad/dual pad/quad pad mode of operation ? single data rate/double data rate mode of operation ? parallel flash mode ? dma support ? memory mapped read access to connected flash devices ? multi-master access with priority and flexible and configurable buffer for each master sai1 sai2 sai3 ? ? the sai module provides a synchronous audio interface (sai) that supports full duplex serial interfaces with frame synchronization, su ch as i2s, ac97, tdm, and codec/dsp interfaces. table 2. i.mx 6ull modules list (continued) block mnemonic block name su bsystem brief description modules list i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 15 sdma smart direct memory access system control peripherals the sdma is multi-channel flexible dma engine. it helps in maximizing system pe rformance by off-loading the various cores in dynamic data routing. it has the following features: ? powered by a 16-bit instruction-set micro-risc engine ? multi-channel dma supporting up to 32 time-division multiplexed dma channels ? 48 events with total flexibility to trigger any combination of channels ? memory accesses including linear, fifo, and 2d addressing ? shared peripherals between arm and sdma ? very fast context-switching with 2-level priority based preemptive multi-tasking ? dma units with auto-flush and prefetch capability ? flexible address management for dma transfers (increment, decrement, and no address changes on source and destination address) ? dma ports can handle unit-directional and bi-directional flows (copy mode) ? up to 8-word buffer for configurable burst transfers for emiv2.5 ? support of byte-swapping and crc calculations ? library of scripts and api is available sjc system jtag controller system control peripherals the sjc provides jtag interface, which complies with jtag tap standards, to internal logic. the i.mx 6ull processors use jtag port for production, testing, and system debugging. in additi on, the sjc provides bsr (boundary scan register) standard support, which complies with ieee1149.1 and ieee1149.6 standards. the jtag port must be accessible during platform initial laboratory bring-up, for manufacturing tests and troubleshooting, as well as for software debugging by authorized entities. the i.mx 6ull sjc incorporates three security modes for protecting against unauthorized accesses. modes are selected through efuse configuration. snvs secure n on-volatile storage security secure non-volatile storage, including secure real time clock, security st ate machine, master key control, and violation/tamper detection and reporting. spdif sony philips digital interconnect format multimedia peripherals a standard audio file transfer format, developed jointly by the sony and phillips corporations. has transmitter and receiver functionality. system counter ? ? the system counter module is a programmable system counter which provides a shared time base to the cortex a series cores as part of arm?s generic timer architecture. it is intended for use in application where the counter is always powered on and supports multiple, unrelated clocks. table 2. i.mx 6ull modules list (continued) block mnemonic block name su bsystem brief description i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 16 nxp semiconductors modules list tsc touch screen touch controller with touch controller to support 4-wire and 5-wire resistive touch panel. tzasc trust-zone address space controller security the tzasc (tzc-380 by arm) provides security address region control functions required for intended application. it is used on the path to the dram controller. uart1 uart2 uart3 uart4 uart5 uart6 uart7 uart8 uart interface connectivity peripherals each of the uartv2 module supports the following serial data transmit/receive protocols and configurations: ? 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even, odd or none) ? programmable baud rates up to 5 mbps. ? 32-byte fifo on tx and 32 half-word fifo on rx supporting auto-baud usdhc1 usdhc2 sd/mmc and sdxc enhanced multi-media card / secure digital host controller connectivity peripherals i.mx 6ull specific soc characteristics: all four mmc/sd/sdio controller ips are identical and are based on the usdhc ip. they are: ? fully compliant with mmc command/response sets and physical layer as defined in the multimedia card system specification, v4.5/4.2/4.3/4.4/4.41/ including high-capacity (size > 2 gb) cards hc mmc. ? fully compliant with sd command/response sets and physical layer as defined in the sd memory card specifications, v3.0 including high-capacity sdxc cards up to 2 tb. ? fully compliant with sd io command/response sets and interrupt/read-wait mode as defined in the sdio card specification, part e1, v3.0 two ports support: ? 1-bit or 4-bit transfer mode specifications for sd and sdio cards up to uhs-i sdr104 mode (104 mb/s max) ? 1-bit, 4-bit, or 8-bit transfer mode specifications for mmc cards up to 52 mhz in both sdr and ddr modes (104 mb/s max) ? 4-bit or 8-bit transfer mode specifications for emmc chips up to 200 mhz in hs200 mode (200 mb/s max) however, the soc level integration and i/o muxing logic restrict the function ality to the following: ? instances #1 and #2 are primarily intended to serve as interfaces to on-board peripherals. these ports are equipped with ?card detection? and ?write protection? pads and do not support hardware reset. ? all ports can work with 1.8 v and 3.3 v cards. there are two completely independent i/o power domains for ports #1 and #2 in four bit configuration (sd interface). table 2. i.mx 6ull modules list (continued) block mnemonic block name su bsystem brief description modules list i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 17 usb universal serial bus 2.0 connectivity peripherals usbo2 (usb otg1 and usb otg2) contains: ? two high-speed otg 2.0 modules with integrated hs usb phys ? support eight transmit (tx) and eight receive (rx) endpoints, including endpoint 0 wdog1 wdog3 watch dog timer peripherals the watch dog timer supports two comparison points during each counting period. each of the comparison points is configurable to evoke an interrupt to the arm core, and a second point evokes an external event on the wdog line. wdog2 (tz) watch dog (trustzone) timer peripherals the trustzone watchdog (tz wdog) timer module protects against trustzone starvation by providing a method of escaping normal mode and forcing a switch to the tz mode. tz starvati on is a situation where the normal os prevents switch ing to the tz mode. such situation is undesirable as it can compromise the system?s security. once the tz wdog module is activated, it must be serviced by tz software on a periodic basis. if servicing does not take place, the timer times out. upon a time-out, the tz wdog asserts a tz mapped interrupt that forces switching to the tz mode. if it is still not served, th e tz wdog asserts a security violation signal to the csu. the tz wdog module cannot be programmed or deactivated by a normal mode sw. table 2. i.mx 6ull modules list (continued) block mnemonic block name su bsystem brief description i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 18 nxp semiconductors modules list 3.1 special signal considerations table 3 lists special signal considerations for the i.mx 6ull processors. the signal names are listed in alphabetical order. the package contact assign ments can be found in section 6, ?package information and contact assignments " .? signal descriptions are provided in the i.mx 6ull reference manual (imx6ullrm). table 3. special signal considerations signal name remarks ccm_clk1_p/ ccm_clk1_n one general purpose differential high speed clock input/output is provided. it can be used: ? to feed external reference clock to the plls and further to the modules inside soc. ? to output internal soc clock to be used outside the soc as either reference clock or as a functional clock for peripherals. see the i.mx 6ull reference manual (imx6ullrm) for details on the respective clock trees. alternatively one may use single ended signal to drive clk1_p input. in this case corresponding clk1_n input should be tied to the constant volt age level equal 1/2 of the input signal swing. termination should be provided in case of high frequency signals. after initialization, the clk1 input/output can be disa bled (if not used). if unused, either or both of the clk1_n/p pairs may remain unconnected. rtc_xtali/rtc_xtalo if the user wishes to configure rt c_xtali and rtc_xtalo as an rtc oscillator, a 32.768 khz crystal, ( ? 100 k ? esr, 10 pf load) should be connected between rtc_xtali and rtc_xtalo. keep in mind the capacitors implemented on either side of the crystal are about twice the crystal load capacitor. to hit the exact oscillation freq uency, the board capacitors need to be reduced to account for board and chip parasitics. the integr ated oscillation amplifier is self biasing, but relatively weak. care must be taken to limit parasitic leakage from rtc_xtali and rtc_xtalo to either power or ground (>100 m ? ). this will debias the amplifier and cause a reduction of startup margin. typically rtc_xtali and rtc_xtalo should bias to approximately 0.5 v. if it is desired to feed an external low frequency clock into rtc_xtali the rtc_xtalo pin should be remain unconnected or driven wit h a complimentary signal. the logic level of this forcing clock should not exceed vdd_snvs_cap level and the frequency should be <100 khz under typical conditions. in case when high accuracy real time clock are not required, system may use internal low frequency ring oscillator. it is recommended to connect rtc_xtali to gnd and keep rtc_xtalo unconnected. xtali/xtalo a 24.0 mhz crystal should be connected between xtali and xtalo. the crystal must be rated for a maximum drive level of 250 ? w. an esr (equivalent series resistance) of typical 80 ? is recommended. nxp bsp (board support package) software requires 24 mhz on xtali/xtalo. the crystal can be eliminated if an external 24 mh z oscillator is available in the system. in this case, xtalo must be directly driven by the external oscillator and xtali is disconnected. if this clock is used as a reference for usb, t hen there are strict frequency tolerance and jitter requirements. see osc24m chapter and relevant interface specifications chapters for details. dram_vref when using ddr_vref with ddr i/o, the nominal reference voltage must be half of the nvcc_dram supply. the user must tie ddr_vref to a precision external resistor divider. use a 1k ? 0.5% resistor to gnd and a 1 k ? 0.5% resistor to nvcc_dram. shunt each resistor with a closely-mounted 0.1 f capacitor. to reduce supply current, a pair of 1.5 k ? 0.1% resistors can be used. using resistors with recommended tolerances ensures the 2% ddr_vref tolerance (per the ddr3 specification) is maintained when two ddr3 ics plus the i.mx 6ull are drawing current on the resistor divider. modules list i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 19 3.2 recommended connections for unused analog interfaces table 5 shows the recommended connecti ons for unused analog interfaces. zqpad dram calibration resistor 240 ? 1 % used as reference during dram output buffer driver calibration should be connected between this pad and gnd. gpanaio this signal is reserved for nxp manufacturin g use only. this output must remain unconnected. jtag_ nnnn the jtag interface is summarized in ta bl e 4 . use of external resistors is unnecessary. however, if external resistors are used, the user must ensu re that the on-chip pull- up/down configuration is followed. for example, do not use an external pull down on an input that has on-chip pull-up. jtag_tdo is configured with a keeper circuit such that the non-connected condition is eliminated if an external pull resistor is not present. an ex ternal pull resistor on jtag_tdo is detrimental and should be avoided. jtag_mod is referenced as sjc_mod in the i.mx 6ull reference manual. both names refer to the same signal. jtag_mod must be externally connected to gnd for normal operation. termination to gnd through an external pull-down resistor (such as 1 k ? ) is allowed. jtag_mod set to hi configures the jtag interface to mode compliant with ieee1149.1 standard. jtag_mod set to low configures the jtag interface for common sw debug adding all the system taps to the chain. nc these signals are no connect (nc) and should be disconnected by the user. por_b this cold reset negative logic input resets all modules and logic in the ic. may be used in addition to internally generated power on reset signal (logical and, both internal and external signals are considered active low). onoff onoff can be configured in debounce, off to on time, and max time-out configurations. the debounce and off to on time configurations supports 0, 50, 100 and 500 ms. debounce is used to generate the power off interrupt. while in the on st ate, if onoff button is pressed longer than the debounce time, the power off interrupt is generated. off to on time supports the time it takes to request power on after a configured button press time has been reached. while in the off state, if onoff button is pressed longer than the off to on time, the state will transition from off to on. max time-out configuration supports 5, 10, 15 se conds and disable. max time-out configuration supports the time it takes to request power do wn after onoff button has been pressed for the defined time. test_mode test_mode is for nxp factory use. the user must tie this pin directly to gnd. table 4. jtag controller interface summary jtag i/o type on-chip termination jtag_tck input 47 k ? ? pull-up jtag_tms input 47 k ? ? pull-up jtag_tdi input 47 k ? ? pull-up jtag_tdo 3-state output keeper jtag_trstb input 47 k ? ? pull-up jtag_mod input 100 k ? ? pull-up table 3. special signal considerations (continued) signal name remarks i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 20 nxp semiconductors modules list table 5. recommended connections for unused analog interfaces module pad name recommendations if unused ccm ccm_clk1_n, ccm_clk1_p not connect usb usb_otg1_chd_b, usb_otg1_dn, usb_otg1_dp, usb_otg1_vbus, usb_otg2_dn, usb_otg2_dp, usb_otg2_vbus not connect adc adc_vrefh tie to vdda_adc_3p3 vdda_adc_3p3 vdda_adc_3p3 must be powered even if the adc is not used. electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 21 4 electrical characteristics this section provides the device a nd module-level electrical characterist ics for the i.mx 6ull processors. 4.1 chip-level conditions this section provides the device-level el ectrical characteristics for the ic. see table 6 for a quick reference to the individual tables and sections. table 6. i.mx 6ull chip-level conditions for these characteri stics topic appears absolute maximum ratings on page 22 thermal resistance on page 22 operating ranges on page 24 external clock sources on page 26 maximum supply currents on page 27 power modes on page 28 usb phy current consumption on page 31 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 22 nxp semiconductors electrical characteristics 4.1.1 absolute maximum ratings 4.1.2 thermal resistance 4.1.2.1 14 x 14 mm (vm) package thermal resistance table 8 displays the 14 x 14 mm (vm) package thermal resistance data. table 7. absolute maximum ratings parameter description symbol min max unit core supply voltage vddsoc_in -0.3 1.6 v internal supply voltage vddarm_cap vddsoc_cap -0.3 1.4 v gpio supply voltage nvcc_csi nvcc_enet nvcc_gpio nvcc_uart nvcc_lcd nvcc_nand nvcc_sd1 -0.5 3.7 v ddr io supply voltage nvcc_dram -0.4 1.975 1 1 the absolute maximum voltage includes an allowance for 400 mv of overshoot on the io pins. per jedec standards, the allowed signal overshoot must be derated if nvcc_dram exceeds 1.575 v. v vdd_snvs_in supply voltage vdd_snvs_in -0.3 3.6 v vddhigh_in supply voltage vdd_high_in -0.3 3.7 v usb vbus usb_otg1_vbus usb_otg2_vbus ?5.5 v input voltage on usb_otg_dp and usb_otg_dn pins usb_otg1_dp/usb_otg1_dn usb_otg2_dp/usb_otg2_dn -0.3 3.63 v input/output voltage range v in/vout -0.5 ovdd+0.3 2 2 ovdd is the i/o supply voltage. v esd damage immunity: human body model (hbm) charge device model (cdm) vesd ? ? 2000 500 v storage temperature range tstorage -40 150 o c table 8. 14 x 14 (vm) thermal resistance data rating test conditions symbol value unit notes junction to ambient natural convection single-layer board (1s) r ? ja 58.4 o c/w 1,2 junction to ambient natural convection four-layer board (2s2p) r ? ja 37.6 o c/w 1,2,3 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 23 4.1.2.2 9 x 9 mm (vk) package thermal resistance table 9 displays the 9 x 9 mm (vk) thermal resistance data. junction to ambient (@200 ft/min) single layer board (1s) r ? jma 48.6 o c/w 1,3 junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 32.9 o c/w 1,3 junction to board ? r ? jb 21.8 o c/w 4 junction to case ? r ? jc 19.3 o c/w 5 junction to package top natural convection ? jt 2.3 o c/w 6 junction to package bo ttom natural convection ? jb 12.0 o c/w 7 1 junction temperature is a function of die size, on-chip powe r dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissi pation of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 wit h the single layer board horizontal. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistance between the die and the printed circuit b oard per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the co ld plate method (mi l spec-883 method 1012.1). 6 thermal characterization parameter indicating the temperatur e difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characteriza tion parameter is written as psi-jt. 7 thermal characterization parameter indicating the temperatur e difference between package bottom center and the junction temperature per jedec jesd51-12. when gree k letters are not available, the thermal characterization parameter is written as psi-jb table 9. 9 x 9 mm (vk) thermal resistance data rating test conditions symbol value unit notes junction to ambient natural convection single-layer board (1s) r ? ja 65.6 o c/w 1,2 junction to ambient natural convection four-layer board (2s2p) r ? ja 36.2 o c/w 1,2,3 junction to ambient (@200 ft/min) single layer board (1s) r ? jma 51.2 o c/w 1,3 junction to ambient (@200 ft/min) four layer board (2s2p) r ? jma 31.8 o c/w 1,3 junction to board ? r ? jb 17.1 o c/w 4 junction to case ? r ? jc 14.5 o c/w 5 junction to package top natural convection ? jt 0.6 o c/w 6 junction to package bottom natural convection ? jb_csb 11.1 o c/w 7 table 8. 14 x 14 (vm) thermal resistance data (continued) rating test conditions symbol value unit notes i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 24 nxp semiconductors electrical characteristics 4.1.3 operating ranges table 10 provides the operating ranges of the i.mx 6ull processors. for details on the chip's power structure, see the ?power manageme nt unit (pmu)? chapter of the i.mx 6ull reference manual (imx6ullrm). 1 junction temperature is a function of die size, on-chip powe r dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipat ion of other components on the board, and board thermal resistance. 2 per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3 per jedec jesd51-6 with the board horizontal. 4 thermal resistances between the die and the printed circuit boa rd per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5 thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6 thermal characterization parameter indicati ng the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, th e thermal characterization parameter is written as psi-jt. 7 thermal resistance between the die and the central solder balls on the bottom of the package based on simulation. table 10. operating ranges parameter description symbol operating conditions min typ max 1 unit comment run mode: ldo enabled vdd_soc_in a7 core at 792 mhz 1.325 ? 1.5 v vdd_soc_in must be 125 mv higher than the ldo output set point (vdd_arm_cap and vdd_soc_cap) for correct supply voltage regulation. a7 core at 528 mhz and below 1.275 ? 1.5 vdd_arm_cap a7 core at 792 mhz 1.2 1.26 v ? a7 core at 528 mhz 1.15 ? 1.26 a7 core at 396 mhz 1.00 ? 1.26 a7 core at 198 mhz 0.925 ? 1.26 vdd_soc_cap ? 1.15 ? 1.26 v ? run mode: ldo bypassed vdd_soc_in a7 core operations at 528 mhz or below. 1.15 ? 1.26 v a7 core operation above 528 mhz is not supported when ldo is bypassed. electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 25 low power run mode: ldo enabled vdd_soc_in ? 1.275 ? 1.5 v vdd_soc_in must be 125 mv higher than the ldo output set point (vdd_arm_cap and vdd_soc_cap) for correct supply voltage regulation. vdd_soc_cap all pll bypassed, all clocks running at 24 mhz or below 0.925 ? 1.26 v ? vdd_arm_cap 0.925 ? 1.26 v low power run mode: ldo bypassed vdd_soc_in all pll bypassed, all clocks running at 24 mhz or below 0.925 ? 1.26 v ? suspend (dsm) mode vdd_soc_in ? 0.9 ? 1.26 v refer to table 15 low power mode current and power consumption on page -29 vdd_high internal regulator vdd_high_in 2 ? 2.80 ? 3.6 v must match the range of voltages that the rechargeable backup battery supports. backup battery supply range vdd_snvs_in 2, 3 ? 2.40 ? 3.6 v can be combined with vddhigh_in, if the system does not require keeping real time and other data on off state. usb supply voltages usb_otg1_vbus ? 4.40 ? 5.5 v ? usb_otg2_vbus ? 4.40 ? 5.5 v ? ddr i/o supply nvcc_dram lpddr2 1.14 1.2 1.3 v ? ddr3l 1.28 1.35 1.45 v ? ddr3 1.43 1.5 1.575 v ? nvcc_dram2p5 ? 2.25 2.5 2.75 v ? gpio supplies nvcc_csi 2 ?1.651.8, 2.8, 3.3 3.6 v all digital i/o supplies (nvcc_xxxx) must be powered (unless otherwise specified in this data sheet) under normal conditions whether the associated i/o pins are in use or not. nvcc_enet 2 nvcc_gpio 2 nvcc_uart 2 nvcc_lcd 2 nvcc_nand 2 nvcc_sd1 2 a/d converter vdda_adc_3p3 2 ? 3.0 3.15 3.6 v vdda_adc_3p3 must be powered when chip is in run mode, idle mode, or suspend mode. vdda_adc_3p3 should not be powered when chip is in snvs mode. table 10. operating ranges (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 26 nxp semiconductors electrical characteristics table 11 shows on-chip ldo regulators that can supply on-chip loads. 4.1.4 external clock sources each i.mx 6ull processor has two external input system clocks: a low frequency (rtc_xtali) and a high frequency (xtali). the rtc_xtali is used for low-frequency functio ns. it supplies the clock for wake-up circuit, power-down real time clock operati on, and slow system and watch-dog counters. the clock input can be connected to either external oscillator or a crystal usi ng internal oscillator amplif ier. additionally, there is an internal ring oscillator, which can be used instead of the rtc_xt ali if accuracy is not important. the system clock input xtali is used to generate the main system cl ock. it supplies th e plls and other peripherals. the system clock input can be connected to either external oscillator or a crystal using internal oscillator amplifier. table 12 shows the interface frequency requirements. temperature operating ranges junction temperature tj standard commercial -40 ? 105 o c see i.mx 6ull product lifetime usage estimates for information on product lifetime (power-on years) for this processor. 1 applying the maximum voltage results in maximum power consumption and heat generation. nxp recommends a voltage set point = (v min + the supply tolerance). this result in an optimized power/speed ratio. 2 applying the maximum voltage results in shorten lifetime. 3.6 v us age limited to < 1% of the use profile. rest of profile limit ed to below 3.49 v. 3 in setting vdd_snvs_in voltage with regards to charging currents and rtc, refer to the i.mx 6ull hardware development guide (imx6ullhdg). table 11. on-chip ldos 1 and their on-chip loads 1 on-chip ldos are designed to supply i.mx 6ull loads and must not be used to supply external loads. voltage source load comment vdd_high_cap nvcc_dram_2p5 board-lev el connection to vdd_high_cap table 12. external input clock frequency parameter description symbol min typ max unit rtc_xtali oscillator 1,2 1 external oscillator or a crystal with internal oscillator amplifier. 2 the required frequency stability of this clock source is application dependent. for recommendations, see the hardware development guide for i.mx 6ull applications processors (imx6ullhdg). f ckil ? 32.768 3 /32.0 3 recommended nominal frequency 32.768 khz. ?khz xtali oscillator 2,4 4 external oscillator or a fundamental frequency crystal with internal oscillator amplifier. f xtal ?24?mhz table 10. operating ranges (continued) electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 27 the typical values shown in table 12 are required for use with nxp bsps to ensure precise time keeping and usb operation. for rtc_xtali operati on, two clock sources are available. ? on-chip 40 khz ring oscillat or?this clock source has th e following characteristics: ? approximately 25 a more i dd than crystal oscillator ? approximately 50% tolerance ? no external component required ? starts up quicker than 32 khz crystal oscillator ? external crystal os cillator with on-chip support circuit: ? at power up, ring oscillator is utilized. after crystal oscill ator is stable, the clock circuit switches over to the crystal oscillator automatically. ? higher accuracy th an ring oscillator ? if no external crystal is present, then the ring oscillator is utilized the decision of choosing a clock source should be taken based on real-time clock use and precision time-out. 4.1.5 maximum supply currents the data shown in table 13 represent a use case designed specifi cally to show the maximum current consumption possible. all cores ar e running at the defined maximum frequency and are limited to l1 cache accesses only to ensure no pipeline stalls. al though a valid condition, it wo uld have a very limited practical use case, if at all, and be limited to an extremely low dut y cycle unless the intention was to specifically show the wors t case power consumption. see the i.mx 6ull power consumption measurement application note (an45 81) for more details on typical power consumption under various use case definitions. table 13. maximum supply currents power line conditions max current unit vdd_soc_in 792 mhz arm clock based on dhrystone test 500 ma vdd_high_in ? 125 1 ma vdd_snvs_in ? 500 2 ? a usb_otg1_vbus usb_otg2_vbus ?50 3 ma vdda_adc_3p3 100 ohm maximum loading for touch panel 35 ma primary interface (io) supplies nvcc_dram ? (see 4 )? nvcc_dram_2p5 ? 50 ma nvcc_gpio n=16 use maximum io equation 5 ? i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 28 nxp semiconductors electrical characteristics 4.1.6 power modes the i.mx 6ull has the following power modes: ? run mode: cpu is active, some portion of the ch ip can be clock gated or power gated. support multiple voltage/frequency scal ing set point for power saving; ? low power mode: cpu in wfi stat e or power gate, some portion of the chip can be shut off for power saving. the suspend, low powe r idle, system idle are consid er as sub-modes of the run mode; ? snvs mode: only rtc and tamper detection logic is active, with 12 gpios in low power state retention mode; ? off mode: all power rails are off. the following table summarizes the external power supply state in all the power modes. nvcc_uart n=16 use maximum io equation 5 ? nvcc_enet n=16 use maximum io equation 5 ? nvcc_lcd n=29 use maximum io equation 5 ? nvcc_nand n=17 use maximum io equation 5 ? nvcc_sd n=6 use maximum io equation 5 ? nvcc_csi n=12 use maximum io equation 5 ? misc dram_vref ? 1 ma 1 the actual maximum current drawn from vdd_high_in will be as shown plus any additional current drawn from the vdd_high_cap outputs, depending upon actual application configuration (for example, nvcc_dram_2p5 supplies). 2 the maximum vdd_snvs_in current may be higher depending on specific operating configurations, such as boot_mode[1:0] not equal to 00, or use of the tamper feature. during initial power on, vdd_snvs_in can draw up to 1 ma, if available. vdd_snvs_cap charge time will increase if less than 1 ma is available. 3 this is the maximum current per active usb physical interface. 4 the dram power consumption is dependent on several factors, such as external signal termination. dram power calculators are typically available from the memory vendors. th ey take in account factors, such as signal termination. see the i.mx 6ull power consumption measurement application note (an4581) or examples of dram power consumption during specific use case scenarios. 5 general equation for estimated, maximum power consumption of an io power supply: imax = n x c x v x (0.5 x f) where: n?number of io pins supplied by the power line c?equivalent external capacitive load v?io voltage (0.5 xf)?data change rate. up to 0.5 of the clock rate (f) in this equation, imax is in amps, c in farads, v in volts, and f in hertz. table 13. maximum supply currents (continued) power line conditions max current unit electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 29 4.1.6.1 run mode in run mode, the cpu is active and running, and th e analog / digital peripher al modules inside the processor will be enabled. in this m ode, all the external power rails to th e processor have to be on and the soc will be able to draw as many current. typically, when the cpu is doing dvfs, it sw itches the vdd_arm voltage according to table 10 . 4.1.6.2 low power mode when the cpu is not running, the pr ocessor can enter low power mode . i.mx 6ull proc essor supports a very flexible set of power mode configurations in low power mode. typically there are three low power modes use d, system idle, low power idle, and suspend: ? system idle?this is a mode that the cpu can automatically enter when there is no thread running. all the peripherals can keep working and the cpu?s state is retained so the interrupt response can be very short. the cores are able to individually enter the wait state. ? low power idle?this mode is for the case when the system needs to have lower power but still keep some of the peripherals alive. most of the peripherals, analog modul es, and phys are shut off. the interrupt response in this mode is exp ected to be longer than the system idle, but its power is much lower. ? suspend?this mode has the greatest power savings; all clocks, unused analog/phys, and peripherals are off. the external dram stays in self-refresh mode. the exit time from this mode is much longer. table 15 shows the current core consump tion (not including i/o) of i.mx 6ull processors in selected low power modes. table 14. power supply state in power modes power rail run low power snvs off vdd_soc_in on on off off vdd_high_in on on off off vdd_snvs on on on off usb_otg1_vbus usb_otg2_vbus on / off on / off off off nvcc_dram_2p5 on on off off vdda_adc_3p3 on / off on / off off off nvcc_dram on on off off nvcc_xxx on / off on / off off off table 15. low power mode current and power consumption mode test conditions supply typical units i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 30 nxp semiconductors electrical characteristics system idle: ldo enabled ? ldo_arm and ldo_soc are set to 1.15 v ? ldo_2p5 set to 2.5 v, ldo_1p1 set to 1.1 v ? cpu in wfi, cpu clock gated ? ddr is in self refresh ? 24 mhz xtal is on ? 528 pll is active, other plls are power down ? high-speed peripheral clock gated, but remain powered vdd_soc_in (1.325 v) 9 ma vdd_high_in (3.0 v) 9.7 vdd_snvs_in (3.0 v) 0.04 total 41.15 mw system idle: ldo bypassed ? ldo_arm and ldo_soc are set to bypass mode ? ldo_2p5 set to 2.5 v, ldo_1p1 set to 1.1 v ? cpu in wfi, cpu clock gated ? ddr is in self refresh ? 24 mhz xtal is on ? 528 pll is active, other plls are power down ? high-speed peripheral clock gated, but remain powered vdd_soc_in (1.25 v) 8.5 ma vdd_high_in (3.0 v) 8.8 vdd_snvs_in (3.0 v) 0.04 total 37.15 mw low power idle: ldo enabled ? ldo_soc is set to 1.15 v, ldo_arm is in pg mode ? ldo_2p5 and ldo_1p1 are set to weak mode ? cpu in power gate mode ? ddr is in self refresh ? all plls are power down ? 24 mhz xtal is off, 24 mhz rcosc used as clock source ? high-speed peripheral are powered off vdd_soc_in (1.025 v) 1.6 ma vdd_high_in (3.0 v) 1.25 vdd_snvs_in (3.0 v) 0.03 to t a l 5 . 4 8 m w low power idle: ldo bypassed ? ldo_soc is in bypass mode, ldo_arm is in pg mode ? ldo_2p5 and ldo_1p1 are set to weak mode ? cpu in power gate mode ? ddr is in self refresh ? all plls are power down ? 24 mhz xtal is off, 24 mhz rcosc used as clock source ? high-speed peripheral are powered off vdd_soc_in (0.9 v) 1.5 ma vdd_high_in (3.0 v) 0.3 vdd_snvs_in (3.0 v) 0.05 total 2.4 mw suspend: ? ldo_soc is in bypass mode, ldo_arm is in pg mode ? ldo_2p5 and ldo_1p1 are shut off ? cpu in power gate mode ? ddr is in self refresh ? all plls are power down ? 24 mhz xtal is off, 24 mhz rcosc is off ? all clocks are shut off, except 32 khz rtc ? high-speed peripheral are powered off vdd_soc_in (0.9 v) 0.3 ma vdd_high_in (3.0 v) 0.03 vdd_snvs_in (3.0 v) 0.03 to t a l 0 . 4 5 m w snvs: ? all soc digital logic, analog module are shut off ? 32 khz rtc is alive ? tamper detection circuit remains active vdd_soc_in (0 v) 0 ma vdd_high_in (0 v) 0 vdd_snvs_in (3.0 v) 0.03 to t a l 0 . 0 9 m w table 15. low power mode current and power consumption (continued) electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 31 4.1.6.3 snvs mode snvs mode is also called rtc m ode, where only the power for the snvs domain remain on. in this mode, only the rtc and tamper de tection logic is still active. the power consumption in snvs mode l with all the tamper detection logic enable d will be less than 0.03 ? ma@3.0v on vdd_snvs for typical silicon at 25c. in snvs mode, the supported wakeup source are rtc alarm, onoff event, and also the 12 gpio pads in vdd_snvs_in domain. in some applications, the snvs mode is powered by non-rechargeable coin cel l battery, so the power consumption in snvs mode has to be very low. 4.1.6.4 off mode in off mode, all power rails are shut off. 4.1.7 usb phy current consumption 4.1.7.1 power down mode in power down mode, everything is powered down, in cluding the usb vbus vali d detectors in typical condition. table 16 shows the usb interface current consumption in power down mode. note the currents on the vdd_high_ cap and vdd_usb_cap were identified to be the voltage divider circuits in the usb-specific level shifters. 4.2 power supplies requir ements and restrictions the system design must comply with power-up sequence, power-down seque nce, and steady state guidelines as described in this sect ion to guarantee the reliab le operation of the devi ce. any deviation from these sequences may result in the following situations: ? excessive current during power-up phase ? prevention of the device from booting ? irreversible damage to the pr ocessor (worst-case scenario) table 16. usb phy current consumption in power down mode vdd_usb_cap (3.0 v) vdd_high_cap (2.5 v) nvcc_pll (1.1 v) current 5.1 ? a 1.7 ? a < 0.5 ? a i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 32 nxp semiconductors electrical characteristics 4.2.1 power-up sequence the below restrictions must be followed: ? vdd_snvs_in supply must be turned on before any other power supply. ? if a coin cell is used to power vdd_snvs_in, th en ensure that it is connected before any other supply is switched on. ? vdd_high_in should be turned on before vdd_soc_in. note the por_b input (if used) must be im mediately asserted at power-up and remain asserted until after the last power rail reaches its working voltage. in the absence of an external reset feed ing the por_b input, the internal por module takes control. see the i.mx 6ull reference manual (imx6ullrm) for further details and to ensure that all necessary requirements are being met. note need to ensure that there is no back voltage (leakage) from any supply on the board towards the 3.3 v supply (f or example, from the external components that use both the 1.8 v and 3.3 v supplies). note usb_otg1_vbus and usb_otg2_vbu s are not part of the power supply sequence and may be powered at any time. 4.2.2 power-down sequence the following restricti ons must be followed: ? vdd_snvs_in supply must be turned off after any other power supply. ? if a coin cell is used to power vdd_snvs_in, then ensure that it is removed after any other supply is switched off. ? vdd_high_in should be turned off after vdd_soc_in is switched off. 4.2.3 power supplies usage all i/o pins should not be externally driven while the i/o power supply for the pin (nvcc_xxx) is off. this can cause internal latch-up a nd malfunctions due to reverse curren t flows. for info rmation about i/o power supply of each pin, s ee ?power rail? columns in pin list tables of section 6, ?package information and contact assignments " .? 4.3 integrated ldo voltage regulator parameters various internal supplies can be powered on from inte rnal ldo voltage regulators. all the supply pins named *_cap must be connected to external capaci tors. the onboard ldos are intended for internal use electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 33 only and should not be used to power any external circuitry. see the i.mx 6ull reference manual (imx6ullrm) for details on the power tree scheme. note the *_cap signals should not be power ed externally. these signals are intended for internal ldo operation only. 4.3.1 digital regulators (ldo_arm, ldo_soc) there are two digital ldo regulators (? digital?, because of the logic loads that they drive, not because of their construction). the advantages of the regulators are to reduce the input s upply variation because of their input supply ripple rejection and their on-die trim ming. this translates into more stable voltage for the on-chip logics. these regulators have two basic modes: ? power gate. the regulation fet is switched full y off limiting the current draw from the supply. the analog part of the regulator is powered down here limiting th e power consumption. ? analog regulation mode. the regulation fet is c ontrolled such that the output voltage of the regulator equals the programmed ta rget voltage. the target voltage is fully programmable in 25 mv steps. for additional information, see the i.mx 6ull reference manual (imx6ullrm). 4.3.2 analog regulators (ldo _1p1, ldo_2p5, and ldo_usb) 4.3.2.1 ldo_1p1 the ldo_1p1 regulator implements a programmable linear-regulator function from vdd_high_in (see table 10 for minimum and maximum input requirements). typical progr amming operating range is 1.0 v to 1.2 v with the nominal defaul t setting as 1.1 v. the ldo_1p1 s upplies the usb phy, and plls. a programmable brown-out detector is included in the regulator that can be used by the system to determine when the load capability of the regulator is being ex ceeded to take the necessary steps. current-limiting can be enabled to allow for in-rus h current requirements during start- up, if needed. active-pull-down can also be enabled for systems requiring this feature. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6ull applications processors (imx6ullhdg). for additional information, see the i.mx 6ull reference manual (imx6ullrm). 4.3.2.2 ldo_2p5 the ldo_2p5 module implements a programmable linear-regulator f unction from vdd_high_in (see table 10 for minimum and maximum input requirement s). typical programming operating range is 2.25 v to 2.75 v with the nominal default setting as 2.5 v. ldo_2p5 supplies the ddr ios, usb phy, e-fuse module, and plls. a programma ble brown-out detector is include d in the regulator that can be used by the system to determine when the load capabili ty of the regulator is being exceeded, to take the i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 34 nxp semiconductors electrical characteristics necessary steps. current-limiting can be enabled to allow for in-rush current requirements during start-up, if needed. active-pull-down can also be enabled for sy stems requiring this feature. an alternate self-biased low-precision weak-regulator is included that can be enabled for applications ne eding to keep the output voltage alive during low-power modes where the main re gulator driver and its a ssociated global bandgap reference module are disabl ed. the output of the weak -regulator is not programmable and is a function of the input supply as well as the load current. typically, with a 3 v input supply the weak-regulator output is 2.525 v and its output impeda nce is approximately 40 ? .. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6ull applications processors (imx6ullhdg). for additional information, see the i.mx 6ull reference manual (imx6ullrm). 4.3.2.3 ldo_usb the ldo_usb module implements a programmable linear-regulator function from the usb vusb voltages (4.4 v?5.5 v) to produce a nominal 3.0 v output voltage. a pr ogrammable brown-out detector is included in the regulator that can be used by the sy stem to determine when the load capability of the regulator is being exceeded, to take the necessary steps. this regul ator has a built in pow er-mux that allows the user to select to run the regulator from either usb vbus supply, when both are present. if only one of the usb vbus voltages is present, then, the regulat or automatically selects th is supply. current limit is also included to help the system meet in-rush current targets. for information on external capacitor requirements fo r this regulator, see the hardware development guide for i.mx 6ull applications processors (imx6ullhdg). for additional information, see the i.mx 6ull reference manual (imx6ullrm). 4.4 pll?s electrical characteristics 4.4.1 audio/video pll?s electrical parameters table 17. audio/video pll?s electrical parameters parameter value clock output range 650 mhz ~1.3 ghz reference clock 24 mhz lock time <11250 reference cycles electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 35 4.4.2 528 mhz pll 4.4.3 ethernet pll 4.4.4 480 mhz pll 4.4.5 arm pll table 18. 528 mhz pll?s electrical parameters parameter value clock output range 528 mhz pll output reference clock 24 mhz lock time <11250 reference cycles table 19. ethernet pll?s electrical parameters parameter value clock output range 500 mhz reference clock 24 mhz lock time <11250 reference cycles table 20. 480 mhz pll?s electrical parameters parameter value clock output range 480 mhz pll output reference clock 24 mhz lock time <383 reference cycles table 21. arm pll?s electrical parameters parameter value clock output range 648 mhz ~ 1296 mhz reference clock 24 mhz lock time <2250 reference cycles i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 36 nxp semiconductors electrical characteristics 4.5 on-chip oscillators 4.5.1 osc24m this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement an oscillator. th e oscillator is powered from nvcc_pll. the system crystal oscillator consists of a pierce-t ype structure running off the digital supply. a straight forward biased-inverter implementation is used. 4.5.2 osc32k this block implements an amplifier that when combined with a suitable quartz crystal and external load capacitors implement a low power oscillator. it also implements a power mux such that it can be powered from either a ~3 v backup battery (vdd_snvs_in) or vdd_high_in such as the oscillator consumes power from vdd_high_in when that supply is available and transitions to the backup battery when vdd_high_in is lost. in addition, if the clock monitor dete rmines that the osc32k is not pres ent, then the source of the 32 k will automatically switch to a crude internal ring oscillator. the frequency range of this block is approximately 10?45 khz. it highly depends on the process, voltage, and temperature. the osc32k runs from vdd_snvs_cap supply, which comes from the vdd_high_in/vdd_snvs_in. the target battery is a ~3 v coin cell. proper choice of coin cell type is necessary for chosen vdd_high _in range. appropriate series resi stor (rs) must be used when connecting the coin cell. rs depends on the charge curr ent limit that depends on the chosen coin cell. for example, for panasonic ml621: ? average discharge voltage is 2.5 v ? maximum charge current is 0.6 ma for a charge voltage of 3.2 v, rs = (3.2-2.5)/0.6 m = 1.17 k. table 22. osc32k main characteristics min typ max comments fosc ? 32.768 khz ? this frequency is nominal and determined mainly by the crystal selected. 32.0 k would work as well. current consumption ? 4 ? a ? the 4 ? a is the consumption of the oscillator alone (osc32k). total supply consumption will depend on what the di gital portion of the rtc consumes. the ring oscillator consumes 1 ? a when ring oscillator is inactive, 20 ? a when the ring oscillator is running. another 1.5 ? a is drawn from vdd_rtc in the power_detect block. so, the total current is 6.5 ? a on vdd_rtc when the ring oscillator is not running. bias resistor ? 14 m ? ? this the integrated bias resistor th at sets the amplifier into a high gain state. any leakage through the esd network, external board leakage, or even a scope probe that is significant relative to this value will debias the amp. the debiasing will result in low gain, and will impact the circuit's ability to start up and maintain oscillations. electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 37 4.6 i/o dc parameters this section includes the dc parame ters of the following i/o types: ? general purpose i/o (gpio) ? double data rate i/o (ddr) for lpddr2 and ddr3/ddr3l modes note the term ?ovdd? in this section refers to the associated supply rail of an input or output. figure 3. circuit for parameters voh and vol for i/o cells 4.6.1 xtali and rtc_xtali (clock inputs) dc parameters table 23 shows the dc parameters for the clock inputs. crystal properties cload ? 10 pf ? usually crystals can be purchased tuned for different cloads. this cload value is typically 1/2 of the capacitances realized on the pcb on either side of the quartz. a higher cload will decrease oscillation margin, but increases current oscillat ing through the crystal. esr ? 50 k ? 100 k ? equivalent series resistance of the crystal. choosing a crystal with a higher value will decrease the oscillating margin. table 23. xtali and rtc_xtali dc parameters 1 parameter symbol test conditions min max unit xtali high-level dc input voltage vih ? 0.8 x nvcc_pll nvcc_pll v xtali low-level dc input voltage vil ? 0 0.2 v rtc_xtali high-level dc input voltage vih ? 0.8 1.1 v rtc_xtali low-level dc input voltage vil ? 0 0.2 v table 22. osc32k main characteristics min typ max comments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 38 nxp semiconductors electrical characteristics 4.6.2 single voltage general purp ose i/o (gpio) dc parameters table 24 shows dc parameters for gp io pads. the parameters in table 24 are guaranteed per the operating ranges in table 10 , unless otherwise noted. 1 the dc parameters are for external clock input only. table 24. single voltage gpio dc parameters parameter symbol test conditions min max units high-level output voltage 1 1 overshoot and undershoot conditions (transitions above ovdd and below gnd) on switching pads must be held below 0.6 v, and the duration of the overshoot/undershoot must not exceed 10% of the system clock cycle. overshoot/ undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. non-compliance to this specification may affect device reliability or cause permanent damage to the device. v oh ioh= -0.1ma (ipp_dse=001,010) ioh= -1ma (ipp_dse=011,100,101,110,111) ovdd-0.15 ? v low-level output voltage 1 vol iol= 0.1ma (ipp_dse=001,010) iol= 1ma (ipp_dse=011,100,101,110,111) ?0.15v high-level input voltage 1,2 2 to maintain a valid level, the transition edge of the input must sustain a constant slew rate (monotonic) from the current dc level through to the target dc level, vil or vih. monotonic input transition time is from 0.1 ns to 1 s. vih ? 0.7 x ovdd ovdd v low-level input voltage 1,2 vil ? 0 0.3 x ovdd v input hysteresis (ovdd= 1.8v) vhys_lowvdd ovdd=1.8v 200 ? mv input hysteresis (ovdd=3.3v vhys_highvdd ovdd=3.3v 200 ? mv schmitt trigger vt+ 2,3 3 hysteresis of 250 mv is guaranteed over all operating conditions when hysteresis is enabled. vth+ ? 0.5 x ovdd ? mv schmitt trigger vt- 2,3 vth- ? ? 0.5 x ovdd mv pull-up resistor (22_k ? pu) rpu_22k vin=0v ? 212 ua pull-up resistor (22_k ? pu) rpu_22k vin=ovdd ? 1 ua pull-up resistor (47_k ? pu) rpu_47k vin=0v ? 100 ua pull-up resistor (47_k ? pu) rpu_47k vin=oovdd ? 1 ua pull-up resistor (100_k ? pu) rpu_100k vin=0v ? 48 ua pull-up resistor (100_k ? pu) rpu_100k vin=ovdd ? 1 ua pull-down resistor (100_k ? pd) rpd_100k vin=ovdd ? 48 ua pull-down resistor (100_k ? pd) rpd_100k vin=0v ? 1 ua input current (no pu/pd) iin vi = 0, vi = ovdd -1 1 ua keeper circuit resistance r_keeper vi =0.3 x ovdd, vi = 0.7 x ovdd 105 175 k ? electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 39 4.6.3 ddr i/o dc parameters the ddr i/o pads support lpddr2 and ddr3/ddr3l operational m odes. for details on supported ddr memory configurations, see section 4.10, ?multi-mode ddr controller (mmdc) ". mmdc operation with the standards stated above is contingent upon th e board ddr design adherence to the ddr design and layout requirements stated in the hardware development guide for the i.mx 6ull applications processor (imx6ullhdg). 4.6.3.1 lpddr2 mode i/o dc parameters 4.6.3.2 ddr3/ddr3l mode i/o dc parameters the parameters in table 27 are guaranteed per the operating ranges in table 10 , unless otherwise noted. table 25. lpddr2 i/o dc electrical parameters 1 1 note that the jedec lpddr2 specification (jesd209_ 2b) supersedes any specification in this document. parameters symbol test conditions min max unit high-level output voltage voh ioh= -0.1ma 0.9 x ovdd ? v low-level output voltage vol iol= 0.1ma ? 0.1 x ovdd v input reference voltage vref ? 0.49 x ovdd 0.51 x ovdd v dc high-level input voltage vih_dc ? vref+0.13 ovdd v dc low-level input voltage vil_dc ? ovss vref-0.13 v differential input logic high vih_diff ? 0.26 note 2 2 the single-ended signals need to be within the respective limits (vih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. ? differential input logic low vil_diff ? note 2 -0.26 ? pull-up/pull-down impedance mismatch mmpupd ? -15 15 % 240 ? unit calibration resolution rres ? ? 10 ? keeper circuit resistance rkeep ? 110 175 k ? input current (no pull-up/down) iin vi = 0, vi = ovdd -2.5 2.5 ? a table 27. ddr3/ddr3l i/o dc electrical characteristics parameters symbol test conditions min max unit high-level output voltage voh ioh= -0.1ma voh (for ipp_dse=001) 0.8 x ovdd 1 ?v low-level output voltage vol iol= 0.1ma vol (for ipp_dse=001) 0.2 x ovdd ? v high-level output voltage voh ioh= -1ma voh (for all except ipp_dse=001) 0.8 x ovdd ? v low-level output voltage vol iol= 1ma vol (for all except ipp_dse=001) 0.2 x ovdd ? v i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 40 nxp semiconductors electrical characteristics 4.6.4 lvds i/o dc parameters the lvds interface complies with tia/eia 644-a standard. see tia/eia standard 644-a, ?electrical characteristics of low voltage differential signaling (lvd s) interface circuits? for details. table 28 shows the low voltage differential signaling (lvds) i/o dc parameters. 4.7 i/o ac parameters this section includes the ac parame ters of the following i/o types: ? general purpose i/o (gpio) ? double data rate i/o (ddr) for lpddr2 and ddr3/ddr3l modes the gpio and ddr i/o load circuit and out put transition time waveforms are shown in figure 4 and figure 5 . input reference voltage vref ? 0.49 x ovdd 0.51 x ovdd v dc high-level input voltage vih_dc ? vref 2 +0.1 ovdd v dc low-level input voltage vil_dc ? ovss vref-0.1 v differential input logic high vih_diff ? 0.2 see note 3 v differential input logic low vil_diff ? ? -0.2 v termination voltage vtt vtt tracki ng ovdd/2 0.49 x ovdd 0.51 x ovdd v pull-up/pull-down impedance mismatch mmpupd ? -10 10 % 240 ?? unit calibration resolution rres ? ? 10 ? keeper circuit resistance rkeep ? 105 165 k ? input current (no pull-up/down) iin vi = 0,vi = ovdd -2.9 2.9 ? a 1 ovdd ? i/o power supply (1.425 v?1.575 v for ddr3 and 1.283 v?1.45 v for ddr3l) 2 vref ? ddr3/ddr3l external reference voltage 3 the single-ended signals need to be within the respective limits (v ih(dc) max, vil(dc) min) for single-ended signals as well as the limitations for overshoot and undershoot. table 28. lvds i/o dc characteristics parameter symbol test conditions min typ max unit output differential voltage vod rload-100 ? diff 250 350 450 mv output high voltage voh ioh = 0 ma 1.25 1.375 1.6 v output low voltage vol iol = 0 ma 0.9 1.025 1.25 v offset voltage vos ? 1.125 1.2 1.375 v table 27. ddr3/ddr3l i/o dc electrical characteristics (continued) parameters symbol test conditions min max unit electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 41 figure 4. load circuit for output figure 5. output transition time waveform 4.7.1 general purpose i/o ac parameters the i/o ac parameters for gpio in slow and fast modes are presented in the table 29 and table 30 , respectively. note that the fast or slow i/o behavior is determined by the appropriate control bits in the iomuxc control registers. table 29. general purpose i/o ac parameters 1.8 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=111) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 2.72/2.79 1.69/1.82 ns output pad transition times, rise/fall (high drive, ipp_dse=101) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 3.99/4.44 2.14/2.50 output pad transition times, rise/fall (medium drive, ipp_dse=100) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 4.52/5.01 2.52/3.07 output pad transition times, rise/fall (low drive. ipp_dse=011) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 5.15/5.68 3.44/3.73 input transition times 1 1 hysteresis mode is recommended for input s with transition times greater than 25 ns. trm ? ? ? 25 ns te s t p o i n t from output under test cl cl includes package, probe and fixture capacitance 0v ovdd 20% 80% 80% 20% tr tf output (at pad) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 42 nxp semiconductors electrical characteristics 4.7.2 ddr i/o ac parameters the ddr i/o pads support lpddr2 and ddr3/ddr3l operational m odes. for details on supported ddr memory configurations, see section 4.10, ?multi-mode ddr controller (mmdc) ". mmdc operation with the standards stated above is contingent upon th e board ddr design adherence to the ddr design and layout requirements stated in the hardware development guide for the i.mx 6ull applications processor (imx6ullhdg). table 31 shows the ac parameters for ddr i/o operating in lpddr2 mode. table 30. general purpose i/o ac parameters 3.3 v mode parameter symbol test condition min typ max unit output pad transition times, rise/fall (max drive, ipp_dse=101) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 1.84/2.06 1.09/1.35 ns ns output pad transition times, rise/fall (high drive, ipp_dse=011) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 2.44/2.75 1.75/2.02 output pad transition times, rise/fall (medium drive, ipp_dse=010) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 3.26/3.70 2.47/2.92 output pad transition times, rise/fall (low drive. ipp_dse=001) tr, tf 22 pf cload, slow slew rate 22 pf cload, fast slew rate ?? 5.26/6.19 4.88/5.77 input transition times 1 1 hysteresis mode is recommended for inputs with transition times greater than 25 ns. trm ? ? ? 25 ns table 31. ddr i/o lpddr2 mode ac parameters 1 parameter symbol test condition min max unit ac input logic high vih(ac) ? vref + 0.22 ovdd v ac input logic low vil(ac) ? 0 vref - 0.22 v ac differential input high voltage 2 vidh(ac) ? 0.44 ? v ac differential input low voltage vidl(ac) ? ? 0.44 v input ac differential cross point voltage 3 vix(ac) relative to vref -0.12 0.12 v over/undershoot peak vpeak ? ? 0.35 v over/undershoot area (above ovdd or below ovss) varea 400 mhz ? 0.3 v-ns electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 43 table 32 shows the ac parameters for ddr i/o operating in ddr3/ddr3l mode. 4.8 output buffer impedance parameters this section defines the i/o impedan ce parameters of the i.mx 6ull processors for the following i/o types: ? single voltage general purpose i/o (gpio) single output slew rate, measured between vol (ac) and voh (ac) tsr 50 ?? to vref. 5 pf load. drive impedance = 40 ?? 30% 1.5 3.5 v/ns 50 ?? to vref. 5pf load.drive impedance = 60 ?? 30% 12.5 skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz ? 0.1 ns 1 note that the jedec lpddr2 spec ification (jesd209_2b) supersedes an y specification in this document. 2 vid(ac) specifies the input differential voltage | vtr - vcp | requi red for switching, where vtr is the ?true? input signal and v cp is the ?complementary? input signal. the minimum value is equal to vih(ac) - vil(ac). 3 the typical value of vix(ac) is expected to be about 0.5 x ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. table 32. ddr i/o ddr3/ddr3l mode ac parameters 1 1 note that the jedec jesd79_3c specification supersedes any specification in this document. parameter symbol test condition min typ max unit ac input logic high vih(ac) ? vref + 0.175 ? ovdd v ac input logic low vil(ac) ? 0 ? vref - 0.175 v ac differential input voltage 2 2 vid(ac) specifies the input differential voltage | vtr-vcp | requir ed for switching, where vtr is the ?true? input signal and v cp is the ?complementary? input signal. the minimum value is equal to vih(ac) - vil(ac). vid(ac) ? 0.35 ? ? v input ac differential cross point voltage 3 3 the typical value of vix(ac) is expected to be about 0.5 x ovdd. and vix(ac) is expected to track variation of ovdd. vix(ac) indicates the voltage at which differential input signal must cross. vix(ac) relative to vref vref - 0.15 ? vref + 0.15 v over/undershoot peak vpeak ? ? ? 0.4 v over/undershoot area (above ovdd or below ovss) varea 400 mhz ? ? 0.5 v-ns single output slew rate, measured between vol (ac) and voh (ac) tsr driver impedance = 34 ? 2.5 ? 5 v/ns skew between pad rise/fall asymmetry + skew caused by ssn t skd clk = 400 mhz ?? 0.1 ns table 31. ddr i/o lpddr2 mode ac parameters 1 (continued) parameter symbol test condition min max unit i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 44 nxp semiconductors electrical characteristics ? double data rate i/o (ddr) for lpddr2, and ddr3/ddr3l modes note gpio and ddr i/o output driver imp edance is measured with ?long? transmission line of impeda nce ztl attached to i/o pad and incident wave launched into transmission line. rpu/rpd and ztl form a volta ge divider that defines specific voltage of incident wave relative to ovdd. output driver impedance is calculated from this voltage divider (see figure 6 ). figure 6. impedance matching load for measurement ipp_do cload = 1p ztl ? , l = 20 inches predriver pmos (rpu) nmos (rpd) pad ovdd ovss t,(ns) 0 u,(v) ovdd t,(ns) 0 vdd vin (do) vout (pad) u,(v) vref rpu = vovdd - vref1 vref1 ? ztl rpd = ? ztl vref2 vovdd - vref2 vref1 vref2 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 45 4.8.1 single voltage gpio output buffer impedance table 33 shows the gpio output buffer impedance (ovdd 1.8 v). table 34 shows the gpio output buffer impedance (ovdd 3.3 v). 4.8.2 ddr i/o output buffer impedance table 35 shows ddr i/o output buffer impe dance of i.mx 6ull processors. note: 1. output driver impedanc e is controlled across pvts using zq calibration procedure. 2. calibration is done against 240 ? external reference resistor. 3. output driver impedance devi ation (calibration accuracy) is 5% (max/min impedance) across pvts. table 33. gpio output buffer average impedance (ovdd 1.8 v) parameter symbol drive strength (dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 260 130 88 65 52 43 37 ? table 34. gpio output buffer average impedance (ovdd 3.3 v) parameter symbol drive strength (dse) typ value unit output driver impedance rdrv 001 010 011 100 101 110 111 157 78 53 39 32 26 23 ? table 35. ddr i/o output buffer impedance parameter symbol test conditions dse (drive strength) typical unit nvcc_dram=1.5 v (ddr3) ddr_sel=11 nvcc_dram=1.2 v (lpddr2) ddr_sel=10 output driver impedance rdrv 000 001 010 011 100 101 110 111 hi-z 240 120 80 60 48 40 34 hi-z 240 120 80 60 48 40 34 ? i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 46 nxp semiconductors electrical characteristics 4.9 system modules timing this section contains the timing a nd electrical parameters for the modul es in each i.mx 6ull processor. 4.9.1 reset timings parameters figure 7 shows the reset timing and table 36 lists the timing parameters. figure 7. reset timing diagram 4.9.2 wdog reset timing parameters figure 8 shows the wdog reset timing and table 37 lists the timing parameters. figure 8. wdogn_b timing diagram note rtc_xtali is approximately 32 khz. rtc_xtali cycle is one period or approximately 30 ? s. note wdog1_b output signals (for each one of the watchdog modules) do not have dedicated pins, but are muxed out through the iomux. see the iomux manual for detailed information. table 36. reset timing parameters id parameter min max unit cc1 duration of por_b to be qualified as valid. 1 ? rtc_xtali cycle table 37. wdogn_b timing parameters id parameter min max unit cc3 duration of wdogn_b assertion 1 ? rtc_xtali cycle por_b cc1 (input) wdogn_b cc3 (output) electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 47 4.9.3 external interface module (eim) the following subsections pr ovide information on the eim. 4.9.3.1 eim interface pads allocation eim supports 32-bit, 16-bit and 8-bit devices operating in address/data separate or multiplexed modes. table 38 provides eim interface pads al location in different modes. 4.9.3.2 general eim timing-synchronous mode figure 9 , figure 10 , and table 39 specify the timings related to th e eim module. all eim output control signals may be asserted and deasserted by an intern al clock synchronized to the eim_bclk rising edge according to corresponding assert ion/negation control fields. table 38. eim multiplexing 1 1 for more information on configuration ports mentioned in this table, see the i.mx 6ull reference manual. setup non multiplexed address/data mo de multiplexed address/data mode 8 bit 16 bit 16 bit 32 bit mum = 0, dsz = 100 mum = 0, dsz = 101 mum = 0, dsz = 001 mum = 1, dsz = 001 mum = 1, dsz = 011 a[15:0] eim_da[15:0] eim_da[15:0] eim_ da[15:0] eim_da[ 15:0] eim_da[15:0] a[25:16] eim_a[25:16] eim_ a[25:16] eim_a[25:16] eim_a[25:16] eim_d[9:0] d[7:0], eim_eb0 eim_d[7:0] ? eim_d[7:0] eim_da[7:0] eim_da[7:0] d[15:8], eim_eb1 ? eim_d[15:8] eim_d[15:8] ei m_da[15:8] eim_da[15:8] d[23:16], eim_eb2 ????eim_d[7:0] d[31:24], eim_eb3 ????eim_d[15:8] i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 48 nxp semiconductors electrical characteristics , figure 9. eim outputs timing diagram figure 10. eim inputs timing diagram 4.9.3.3 examples of eim synchronous accesses table 39. eim bus timing parameters 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max we1 eim_bclk cycle time 2 t ? 2 x t ? 3 x t ? 4 x t ? we2 eim_bclk low level width 0.4 x t ? 0.8 x t ? 1.2 x t ? 1.6 x t ? we3 eim_bclk high level width 0.4 x t ? 0.8 x t ? 1.2 x t ? 1.6 x t ? we4 eim_addrxx eim_csx_b eim_we_b eim_oe_b eim_bclk eim_ebx_b eim_lba_b output data ... we5 we6 we7 we8 we9 we10 we11 we12 we13 we14 we15 we16 we17 we3 we2 we1 input data eim_wait_b eim_bclk we19 we18 we21 we20 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 49 we4 clock rise to address valid 3 -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 -t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we5 clock rise to address invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we6 clock rise to eim_csx_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we7 clock rise to eim_csx_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we8 clock rise to eim_we_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we9 clock rise to eim_we_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we10 clock rise to eim_oe_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we11 clock rise to eim_oe_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we12 clock rise to eim_ebx_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we13 clock rise to eim_ebx_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we14 clock rise to eim_lba_b valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we15 clock rise to eim_lba_b invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we16 clock rise to output data valid -0.5 x t - 1.25 -0.5 x t + 1.75 -t - 1.25 - t + 1.75 -1.5 x t - 1.25 -1.5 x t +1.75 -2 x t - 1.25 -2 x t + 1.75 we17 clock rise to output data invalid 0.5 x t - 1.25 0.5 x t + 1.75 t - 1.25 t + 1.75 1.5 x t - 1.25 1.5 x t +1.75 2 x t - 1.25 2 x t + 1.75 we18 input data setup time to clock rise 2 ? 4????? we19 input data hold time from clock rise 2 ? 2????? we20 eim_wait_b setup time to clock rise 2 ? 4????? we21 eim_wait_b hold time from clock rise 2 ? 2????? table 39. eim bus timing parameters (continued) 1 id parameter bcd = 0 bcd = 1 bcd = 2 bcd = 3 min max min max min max min max i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 50 nxp semiconductors electrical characteristics figure 11 to figure 14 provide few examples of ba sic eim accesses to external memory devices with the timing parameters mentioned previously fo r specific control parameters settings. figure 11. synchronous memory read access, wsc=1 1 t is the maximum eim logic (axi_clk) cycle time. the maximum allowed axi_clk frequency depends on the fixed/non-fixed latency configuration, whereas the ma ximum allowed eim_bclk frequency is: ?fixed latency for both read and write is 132 mhz. ?variable latency for read only is 132 mhz. ?variable latency for write only is 52 mhz. in variable latency configuration for write, if bcd = 0 & wb cdd = 1 or bcd = 1, axi_clk must be 104 mhz. write bcd = 1 and 104 mhz axi_clk, will result in an eim_bclk of 52 mhz. when the clock branch to eim is decreased to 104 mhz, other buses are impacted which are clocked from th is source. see the ccm chapter of the i.mx 6ull reference manual (imx6ullrm) for a detailed clock tree description. 2 eim_bclk parameters are being measured from the 50% point, that is, high is defined as 50% of signal value and low is defined as 50% as signal value. 3 for signal measurements, ?high? is defined as 80% of si gnal value and ?low? is defined as 20% of signal value. last valid address address v1 d(v1) eim_bclk eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we4 we5 we6 we7 we10 we11 we13 we12 we14 we15 we18 we19 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 51 figure 12. synchronous memory, write access, wsc=1, wbea=0 and wadvn=0 figure 13. muxed address/data (a/d) mode, synchr onous write access, wsc=6, adva=0, advn=1, and adh=1 note in 32-bit muxed address/data (a/d) mode the 16 msbs are driven on the data bus. last valid address address v1 d(v1) eim_bclk eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we4 we5 we6 we7 we8 we9 we12 we13 we14 we15 we16 we17 eim_bclk eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b address v1 write data we4 we16 we6 we7 we9 we8 we10 we11 we14 we15 we17 we5 last valid address eim_addrxx/ eim_adxx i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 52 nxp semiconductors electrical characteristics figure 14. 16-bit muxed a/d mode , synchronous read access, wsc=7, radvn=1, adh=1, oea=0 4.9.3.4 general eim timing-asynchronous mode figure 15 through figure 19 , and table 40 help to determine timing parameters relative to the chip select (cs) state for asynchronous and dt ack eim accesses with corresponding eim bit fi elds and the timing parameters mentioned above. asynchronous read & write access length in cy cles may vary from what is shown in figure 15 through figure 18 as rwsc, oen and csn is configured differently. see the i.mx 6ull reference manual (imx6ullrm) for the eim programming model. figure 15. asynchronous memory read access (rwsc = 5) last eim_bclk eim_addrxx/ eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b address v1 data valid address eim_adxx we5 we6 we7 we14 we15 we10 we11 we12 we13 we18 we19 we4 last valid address address v1 d(v1) eim_addrxx/ eim_dataxx[7:0] eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 int_clk start of access end of access maxdi maxcso maxco eim_adxx electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 53 figure 16. asynchronous a/d muxed read access (rwsc = 5) figure 17. asynchronous memory write access addr. v1 d(v1) eim_addrxx/ eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b we39 we35a we37 we36 we38 we40a we31 we44 int_clk start of access end of access maxdi maxcso maxco we32a eim_adxx eim_we_b eim_oe_b eim_ebx_b eim_csx_b we33 we45 we34 we46 addr. v1 d(v1) eim_addrxx/ we31 we42 we41 we32a eim_dataxx eim_lba_b we39 we40a i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 54 nxp semiconductors electrical characteristics figure 18. asynchronous a/d muxed write access figure 19. dtack mode read access (dap=0) eim_we_b eim_oe_b eim_ebx_b eim_csx_b we33 we45 we34 we46 addr. v1 d(v1) eim_addrxx/ we31 we42 we41 we32a eim_dataxx eim_lba_b we39 we40a last valid address address v1 d(v1) eim_addrxx eim_dataxx[7:0] eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we39 we35 we37 we32 we36 we38 we43 we40 we31 we44 eim_dtack_b we47 we48 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 55 figure 20. dtack mode write access (dap=0) table 40. eim asynchronous timing parameters table relative chip to select ref no. parameter determination by synchronous measured parameters 1 min max (if 132 mhz is supported by soc) unit we31 eim_csx_b valid to address valid we4 - we6 - csa 2 ? 3 - csa ns we32 address invalid to eim_csx_b invalid we7 - we5 - csn 3 ?3 - csnns we32a(m uxed a/d eim_csx_b valid to address invalid t 4 + we4 - we7 + (advn 5 + adva 6 + 1 - csa) -3 + (advn + adva + 1 - csa) ?ns we33 eim_csx_b valid to eim_we_b valid we8 - we6 + (wea - wcsa) ? 3 + (wea - wcsa) ns we34 eim_we_b invalid to eim_csx_b invalid we7 - we9 + (wen - wcsn) ? 3 - (wen_wcsn) ns we35 eim_csx_b valid to eim_oe_b valid we10 - we6 + (oea - rcsa) ? 3 + (oea - rcsa) ns we35a (muxed a/d) eim_csx_b valid to eim_oe_b valid we10 - we6 + (oea + radvn + radva + adh + 1 - rcsa) -3 + (oea + radvn+radva+ adh+1-rcsa) 3 + (oea + radvn+radva+ad h+1-rcsa) ns we36 eim_oe_b invalid to eim_csx_b invalid we7 - we11 + (oen - rcsn) ? 3 - (oen - rcsn) ns we37 eim_csx_b valid to eim_ebx_b valid (read access) we12 - we6 + (rbea - rcsa) ? 3 + (rbea - rcsa) ns last valid address address v1 d(v1) eim_addrxx eim_dataxx eim_we_b eim_lba_b eim_oe_b eim_ebx_b eim_csx_b next address we31 we39 we33 we45 we32 we40 we34 we46 we42 we41 eim_dtack_b we48 we47 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 56 nxp semiconductors electrical characteristics we38 eim_ebx_b invalid to eim_csx_b invalid (read access) we7 - we13 + (rben - rcsn) ? 3 - (rben- rcsn) ns we39 eim_csx_b valid to eim_lba_b valid we14 - we6 + (adva - csa) ? 3 + (adva - csa) ns we40 eim_lba_b invalid to eim_csx_b invalid (advl is asserted) we7 - we15 - csn ? 3 - csn ns we40a (muxed a/d) eim_csx_b valid to eim_lba_b invalid we14 - we6 + (advn + adva + 1 - csa) -3 + (advn + adva + 1 - csa) 3 + (advn + adva + 1 - csa) ns we41 eim_csx_b valid to output data valid we16 - we6 - wcsa ? 3 - wcsa ns we41a (muxed a/d) eim_csx_b valid to output data valid we16 - we6 + (wadvn + wadva + adh + 1 - wcsa) ? 3 + (wadvn + wadva + adh + 1 - wcsa) ns we42 output data invalid to eim_csx_b invalid we17 - we7 - csn ? 3 - csn ns maxco output maximum delay from internal driving eim_addrxx/control ffs to chip outputs 10 ? ? ns maxcso output maximum delay from csx internal driving ffs to csx out 10 ? ? ns maxdi eim_dataxx maximum delay from chip input data to its internal ff 5??ns we43 input data valid to eim_csx_b invalid maxco - maxcso + maxdi maxco - maxcso + maxdi ?ns we44 eim_csx_b invalid to input data invalid 00?ns we45 eim_csx_b valid to eim_ebx_b valid (write access) we12 - we6 + (wbea - wcsa) ? 3 + (wbea - wcsa) ns we46 eim_ebx_b invalid to eim_csx_b invalid (write access) we7 - we13 + (wben - wcsn) ? -3 + (wben - wcsn) ns table 40. eim asynchronous timing parameters table relative chip to select (continued) ref no. parameter determination by synchronous measured parameters 1 min max (if 132 mhz is supported by soc) unit electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 57 4.10 multi-mode ddr controller (mmdc) the multi-mode ddr controller is a dedi cated interface to ddr3/ddr3l/lpddr2 sdram. 4.10.1 mmdc compatibility with jedec-compliant sdrams the i.mx 6ull mmdc supports the following memory types: ? lpddr2 sdram compliant with jesd209-2b lpddr2 jedec standard release june, 2009 ? ddr3/ddr3l sdram compliant with jesd79-3 d ddr3 jedec standard release april, 2008 mmdc operation with the standards stated above is contingent upon th e board ddr design adherence to the ddr design and layout requirements stated in the hardware development guide for the i.mx 6ull applications processor (imx6ullhdg) . 4.10.2 mmdc supported ddr3/ ddr3l/lpddr2 configurations table 41 shows the supported ddr3/ddr 3l/lpddr2 configurations: maxdti maximum delay from eim_dtack_b to its internal ff + 2 cycles for synchronization 10 ? ? ? we47 eim_dtack_b active to eim_csx_b invalid maxco - maxcso + maxdti maxco - maxcso + maxdti ?ns we48 eim_csx_b invalid to eim_dtack_b invalid 00?ns 1 for more information on configuration par ameters mentioned in this table, see the i.mx 6ull reference manual (imx6ullrm). 2 in this table, csa means wcsa when write operation or rcsa when read operation. 3 in this table, csn means wcsn when write operation or rcsn when read operation. 4 t is axi_clk cycle time. 5 in this table, advn means wadvn when write operation or radvn when read operation. 6 in this table, adva means wadva when write operation or radva when read operation. table 41. i.mx 6ull supported ddr3 /ddr3l/lpddr2 co nfigurations parameter ddr3 ddr3l ldddr2 clock frequency 400 mhz 400 mhz 400 mhz bus width 16-bit 16-bit 16-bit channel single single single chip selects 2 2 2 table 40. eim asynchronous timing parameters table relative chip to select (continued) ref no. parameter determination by synchronous measured parameters 1 min max (if 132 mhz is supported by soc) unit i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 58 nxp semiconductors electrical characteristics 4.11 general-purpose media interface (gpmi) timing the i.mx 6ull gpmi controller is a flexible inte rface nand flash controller wi th 8-bit data width, up to 200 mb/s i/o speed and individual chip select. it supports asynchronous timing mode, source synchronous timing mode and samsung toggle timing mode separately described in the following subsections. 4.11.1 asynchronous mode ac ti ming (onfi 1.0 compatible) asynchronous mode ac timings are provided as multipli cations of the clock cycle and fixed delay. the maximum i/o speed of gpmi in as ynchronous mode is about 50 mb/s. figure 21 through figure 24 depicts the relative timing betwee n gpmi signals at the module le vel for different operations under asynchronous mode. table 42 describes the timing parameters (nf1?n f17) that are shown in the figures. figure 21. command latch cycle timing diagram figure 22. address latch cycle timing diagram }uuv . ! . $ ? # , % . ! . $ ? # % ? " . ! . $ ? 7 % ? " . ! . $ ? ! , % . ! . $ ? $ ! 4 ! x x e &? e &? e & e & e &? e &? e & e &? e &e ? ?? e & e & e &? e &? e & e & e &? e & e &? . ! . $ ? # , % . ! . $ ? # % ? " . ! . $ ? 7 % ? " . ! . $ ? ! , % e e z d ?? electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 59 figure 23. write data latch cycle timing diagram figure 24. read data latch cycle timing diagram (non-edo mode) figure 25. read data latch cycle timing diagram (edo mode) table 42. asynchronous mode timing parameters 1 id parameter symbol timing t = gpmi clock cycle unit min. max. nf1 nand_cle setup time tcls (as + ds) ? t - 0.12 [see 2,3 ]ns nf2 nand_cle hold time tclh dh ? t - 0.72 [see 2 ]ns nf3 nand_ce0_b setup time tcs (as + ds + 1) ? t [see 3,2 ]ns nf4 nand_ce0_b hold time tch (dh+1) ? t - 1 [see 2 ]ns nf5 nand_we_b pulse width twp ds ? t [see 2 ]ns ? ?} e & e & e & e & e & e &? e & e &? . ! . $ ? # , % . ! . $ ? # % ? " . ! . $ ? 7 % ? " . ! . $ ? ! , % . ! . $ ? $ ! 4 ! x x e &? e &? ? (?}u e & e &e e &? e & e & e &? e &? . ! . $ ? # , % . ! . $ ? # % ? " . ! . $ ? 2 % ? " . ! . $ ? 2 % ! $ 9 ? " . ! . $ ? $ ! 4 ! x x ? (?}u e & e &e e &? e & e & e &? e &? . ! . $ ? # , % . ! . $ ? # % ? " . ! . $ ? 2 % ? " . ! . $ ? 2 % ! $ 9 ? " e e z d ?? i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 60 nxp semiconductors electrical characteristics in edo mode ( figure 24 ), nf16/nf17 is different from the definition in non-edo mode ( figure 23 ). they are called trea/trhoh (re# access time/re# hi gh to output hold). the typical values for them are 16 ns (max for trea)/15 ns (min for trhoh) at 50 mb/s edo mode. in edo mode, gpmi will sample nand_dataxx at rising edge of delayed nand_re_b provided by an internal dpll. the delay value can be controlled by gpmi_ctr l1.rdn_delay (see the gpmi chapter of the i.mx 6ull reference manual ). the typical value of this control register is 0x8 at 50 mt/s edo mode. but if the board delay is big enough and cannot be ignored, the delay value should be ma de larger to compensate the board delay. 4.11.2 source synchronous mode ac timing (onfi 2.x compatible) figure 26 to figure 28 show the write and read timi ng of source synchronous mode. nf6 nand_ale setup time tals (as + ds) ? t - 0.49 [see 3,2 ]ns nf7 nand_ale hold time talh (dh ? t - 0.42 [see 2 ]ns nf8 data setup time tds ds ? t - 0.26 [see 2 ]ns nf9 data hold time tdh dh ? t - 1.37 [see 2 ]ns nf10 write cycle time twc (ds + dh) ? t [see 2 ]ns nf11 nand_we_b hold time twh dh ? t [see 2 ]ns nf12 ready to nand_re_b low trr 4 (as + 2) ? t [see 3,2 ]?ns nf13 nand_re_b pulse width trp ds ? t [see 2 ]ns nf14 read cycle time trc (ds + dh) ? t [see 2 ]ns nf15 nand_re_b high hold time treh dh ? t [see 2 ]ns nf16 data setup on read tdsr ? (ds ? t -0.67)/18.38 [see 5,6 ]ns nf17 data hold on read tdhr 0.82/11.83 [see 5,6 ]?ns 1 gpmi?s async mode output timing can be controlled by the module?s internal registers hw_gpmi_timing0_address_ setup, hw_gpmi_timing0_ data_setup, and hw_gpm i_timing0_data_hold. this ac timing depends on these registers settings. in the table, as/ds/dh represents each of these settings. 2 as minimum value can be 0, while ds/dh minimum value is 1. 3 t = gpmi clock period -0.075ns (half of maximum p-p jitter). 4 nf12 is guaranteed by the design. 5 non-edo mode. 6 edo mode, gpmi clock ? 100 mhz (as=ds=dh=1, gpmi_ctl1 [rdn_delay] = 8, gpmi_ctl1 [half_period] = 0). table 42. asynchronous mode timing parameters 1 (continued) id parameter symbol timing t = gpmi clock cycle unit min. max. electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 61 figure 26. source synchronous mode command and address timing diagram 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) & 0 ' $ ' ' . ! . $ ? # % ? " 1 $ 1 ' b & / ( 1 $ 1 ' b $ / ( 1 $ 1 ' b : ( 5 ( b % 1 $ 1 ' b & / . 1 $ 1 ' b ' 4 6 1 $ 1 ' b ' 4 6 2 x w s x w h q d e o h 1 $ 1 ' b ' $ 7 $ > @ 1 $ 1 ' b ' $ 7 $ > @ 2 x w s x w h q d e o h i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 62 nxp semiconductors electrical characteristics figure 27. source synchronous mode data write timing diagram figure 28. source synchronous mode data read timing diagram 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) . ! . $ ? # % ? " . ! . $ ? # , % . ! . $ ? ! , % 1 $ 1 ' b : ( 5 ( b % . ! . $ ? # , + . ! . $ ? $ 1 3 . ! . $ ? $ 1 3 2 x w s x w h q d e o h . ! . $ ? $ 1 ; = . ! . $ ? $ 1 ; = 2 x w s x w h q d e o h 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) 1 ) . ! . $ ? # % ? " . ! . $ ? # , % 1 $ 1 ' b $ / ( . ! . $ ? 7 % 2 % . ! . $ ? # , + . ! . $ ? $ 1 3 . ! . $ ? $ 1 3 / u t p u t e n a b l e . ! . $ ? $ ! 4 ! ; = . ! . $ ? $ ! 4 ! ; = / u t p u t e n a b l e 1 ) electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 63 figure 29. nand_dqs/nand_dq read valid window for ddr source sync mode, figure 29 shows the timing diagram of nand_dqs/nand_dataxx read valid window. the typical value of tdqsq is 0.85ns (max) and 1ns (max) for tqhs at 200mb/s. gpmi will sample nand_data[7:0] at both rising and fa lling edge of a delaye d nand_dqs signal, which can be provided by an internal dpll. the dela y value can be controlled by gpmi register gpmi_read_ddr_dll_ctrl.slv_dly_targ et (see the gpmi chapter of the i.mx 6ull reference manual ). generally, the typical delay value of th is register is equal to 0x7 which means 1/4 table 43. source synchronous mode timing parameters 1 1 gpmi?s source synchronous mode output timing can be controlled by the module?s internal registers gpmi_timing2_ce_delay, gpmi_timing_preamble_delay, gpmi_timing2_post_delay. this ac timing depends on these registers settings. in the table, ce_delay/pre _delay/post_delay represents each of these settings. id parameter symbol timing t = gpmi clock cycle unit min. max. nf18 nand_ce0_b access time tce ce_delay ? t - 0.79 [see 2 ] 2 t = tck(gpmi clock period) -0.075ns (half of maximum p-p jitter). ns nf19 nand_ce0_b hold time tch 0.5 ? tck - 0.63 [see 2 ]ns nf20 command/address nand_dataxx setup time tcas 0.5 ? tck - 0.05 ns nf21 command/address nand_dataxx hold time tcah 0.5 ? tck - 1.23 ns nf22 clock period tck ? ns nf23 preamble delay tpre pre_delay ? t - 0.29 [see 2 ]ns nf24 postamble delay tpost post_delay ? t - 0.78 [see 2 ]ns nf25 nand_cle and nand_ale setup time tcals 0.5 ? tck - 0.86 ns nf26 nand_cle and nand_ale hold time tcalh 0.5 ? tck - 0.37 ns nf27 nand_clk to first nand_dqs latching transition tdqss t - 0.41 [see 2 ]ns nf28 data write setup ? 0.25 ? tck - 0.35 ? nf29 data write hold ? 0.25 ? tck - 0.85 ? nf30 nand_dqs/nand_dq read setup skew ? ? 2.06 ? nf31 nand_dqs/nand_dq read hold skew ? ? 1.95 ? ? ? . ! . $ ? $ 1 3 . ! . $ ? $ ! 4 ! ; = e &? e &? e &? e &? i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 64 nxp semiconductors electrical characteristics clock cycle delay expected. but if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 4.11.3 samsung toggle mode ac timing 4.11.3.1 command and address timing note samsung toggle mode command and addr ess timing is the same as onfi 1.0 compatible async mode ac timing. see section 4.11.1, ?asynchronous mode ac timing (onfi 1.0 compatible) " ,? for details. 4.11.3.2 read and write timing figure 30. samsung toggle mode data write timing . ! . $ ? $ ! 4 ! ; = d e v ? c l k . ! . $ ? # % x ? " . ! . $ ? # , % . ! . $ ? ! , % . ! . $ ? 7 % ? " . ! . $ ? 2 % ? " . ! . $ ? $ 1 3 t # + . & . & t # + electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 65 figure 31. samsung toggle mode data read timing table 44. samsung toggle mode timing parameters 1 id parameter symbo l timing t = gpmi clock cycle uni t min. max. nf1 nand_cle setup time tcls (as + ds) ? t - 0.12 [see 2,3 ]? nf2 nand_cle hold time tclh dh ? t - 0.72 [see 2 ]? nf3 nand_ce0_b setup time tcs (as + ds) ? t - 0.58 [see 3,2 ]? nf4 nand_ce0_b hold time tch dh ? t - 1 [see 2 ]? nf5 nand_we_b pulse width twp ds ? t [see 2 ]? nf6 nand_ale setup time tals (as + ds) ? t - 0.49 [see 3,2 ]? nf7 nand_ale hold time talh dh ? t - 0.42 [see 2 ]? nf8 command/address nand_dataxx setup time tcas ds ? t - 0.26 [see 2 ]? nf9 command/address nand_dataxx hold time tcah dh ? t - 1.37 [see 2 ]? nf18 nand_cex_b access time tce ce_delay ? t [see 4,2 ]?ns nf22 clock period tck ? ? ns d e v ? c l k . ! . $ ? # % x ? " . ! . $ ? # , % . ! . $ ? ! , % . ! . $ ? 7 % ? " . ! . $ ? 2 % ? " . ! . $ ? $ 1 3 . ! . $ ? $ ! 4 ! ; = . & t # + t # + . & t # + t # + . & t # + i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 66 nxp semiconductors electrical characteristics for ddr toggle mode, figure 29 shows the timing diagram of nan d_dqs/nand_dataxx read valid window. the typical value of tdqsq is 1.4 ns (max) a nd 1.4 ns (max) for tqhs at 133 mb/s. gpmi will sample nand_data[7:0] at both rising and falling edge of an delayed nand_dqs signal, which is provided by an internal dpll. the delay value of th is register can be cont rolled by gpmi register gpmi_read_ddr_dll_ctrl.slv_dly_targ et (see the gpmi chapter of the i.mx 6ull reference manual ). generally, the typical de lay value is equal to 0x7 whic h means 1/4 clock cycle delay expected. but if the board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the board delay. 4.12 external peripheral interface parameters the following subsections provide inform ation on external peripheral interfaces. 4.12.1 cmos sensor interface (csi) timing parameters 4.12.1.0.1 gated clock mode timing figure 32 and figure 33 shows the gated clock mode timings for csi, and table 45 describes the timing parameters (p1?p7) shown in the figures. a fram e starts with a rising/ falling edge on csi_vsync nf23 preamble delay tpre pre_delay ? t [see 5,2 ]?ns nf24 postamble delay tpost post_delay ? t +0.43 [see 2 ]? ns nf28 data write setup tds 6 0.25 ? tck - 0.32 ? ns nf29 data write hold tdh 6 0.25 ? tck - 0.79 ? ns nf30 nand_dqs/nand_dq read setup skew tdqsq 7 ?3.18? nf31 nand_dqs/nand_dq read hold skew tqhs 7 ?3.27? 1 the gpmi toggle mode output timing can be controlled by the module?s internal registers hw_gpmi_timing0_address_setup, hw_gpmi_timing0_data_setup, and hw_gpmi_timing0_data_hold. this ac timing depends on these registers settings. in the table, as/ds/dh represents each of these settings. 2 as minimum value can be 0, while ds/dh minimum value is 1. 3 t = tck (gpmi clock period) -0.075ns (half of maximum p-p jitter). 4 ce_delay represents hw_gpmi_timing2[ce _delay]. nf18 is guaranteed by the de sign. read/write operation is started with enough time of ale/cle assertion to low level. 5 pre_delay+1) ? (as+ds) 6 shown in figure 30 . 7 shown in figure 31 . table 44. samsung toggle mode timing parameters 1 (continued) id parameter symbo l timing t = gpmi clock cycle uni t min. max. electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 67 (vsync), then csi_hsync (hsync) is asserted and holds for th e entire line. the pixel clock, csi_pixclk (pixclk), is valid as long as hsync is asserted. figure 32. csi gated clock mode?sensor data at falling edge, latch data at rising edge figure 33. csi gated clock mode?sensor data at rising edge, latch data at falling edge table 45. csi gated clock mode timing parameters id parameter symbol min. max. units p1 csi_vsync to csi_hsync time tv2h 33.5 ? ns p2 csi_hsync setup time thsu 1 ? ns p3 csi data setup time tdsu 1 ? ns p4 csi data hold time tdh 1 ? ns p5 csi pixel clock high time tclkh 3.75 ? ns csi_pixclk csi_vsync csi_data[15:00] p5 p1 p3 p4 csi_hsync p2 p6 p7 csi_pixclk csi_vsync csi_data[15:00] p6 p1 p3 p4 csi_hsync p2 p5 p7 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 68 nxp semiconductors electrical characteristics 4.12.1.0.2 ungated clock mode timing figure 34 shows the ungated clock m ode timings of csi, and table 46 describes the timing parameters (p1?p6) that are shown in the figure. in ungated mode the csi_vsync and csi_pixclk signals are used, and the csi_hsync signal is ignored. figure 34. csi ungated clock mode?sensor data at falling edge, latch data at rising edge the csi enables the chip to connect directly to exte rnal cmos image sensors, which are classified as dumb or smart as follows: ? dumb sensors only support traditi onal sensor timing (vertical sync (vsync) and horizontal sync (hsync)) and output-only bayer and statistics data. ? smart sensors support ccir656 vi deo decoder formats and perfor m additional processing of the image (for example, image compression, image pr e-filtering, and various data output formats). p6 csi pixel clock low time tclkl 3.75 ? ns p7 csi pixel clock frequency fclk ? 133.3 mhz table 46. csi ungated clock mode timing parameters id parameter symbol min. max. units p1 csi_vsync to pixel clock time tvsync 33.5 ? ns p2 csi data setup time tdsu 1 ? ns p3 csi data hold time tdh 1 ? ns p4 csi pixel clock high time tclkh 3.75 ? ns p5 csi pixel clock low time tclkl 3.75 ? ns p6 csi pixel clock frequency fclk ? 133.3 mhz table 45. csi gated clock mode timing parameters (continued) id parameter symbol min. max. units csi_pixclk csi_vsync csi_data[15:00] p4 p1 p2 p3 p5 p6 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 69 4.12.2 ecspi timing parameters this section describes the timing parameters of the ecspi blocks. the ecspi have separate timing parameters for master and slave modes. 4.12.2.1 ecspi master mode timing figure 35 depicts the timing of ecspi in master mode. table 47 lists the ecspi master mode timing characteristics. figure 35. ecspi master mode timing diagram table 47. ecspi master mode timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle time?read ecspix_sclk cycle time?write t clk 43 15 ?ns cs2 ecspix_sclk high or low time?read ecspix_sclk high or low time?write t sw 21.5 7 ?ns cs3 ecspix_sclk rise or fall 1 1 see specific i/o ac parameters section 4.7, ?i/o ac parameters " .? t rise/fall ??ns cs4 ecspix_ss_b pulse width t cslh half ecspix_sclk period ? ns cs5 ecspix_ss_b lead time (cs setup time) t scs half ecspix_sclk period - 4 ? ns cs6 ecspix_ss_b lag time (cs hold time) t hcs half ecspix_sclk period - 2 ? ns cs7 ecspix_mosi propagation delay (c load =20pf) t pdmosi -1 1 ns cs8 ecspix_miso setup time t smiso 14 ? ns cs9 ecspix_miso hold time t hmiso 0?ns cs10 rdy to ecspix_ss_b time 2 2 spi_rdy is sampled internally by ipg_clk and is asynchronous to all other cspi signals. t sdry 5?ns cs7 cs2 cs2 cs4 cs6 cs5 cs8 cs9 ecspix_sclk ecspix_ss_b ecspix_mosi ecspix_miso ecspix_rdy_b cs10 cs3 cs3 cs1 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 70 nxp semiconductors electrical characteristics 4.12.2.2 ecspi slave mode timing figure 36 depicts the timing of ecspi in slave mode. table 48 lists the ecspi slave mode timing characteristics. figure 36. ecspi slave mode timing diagram 4.12.3 enhanced serial audio inte rface (esai) timing parameters the esai consists of independent transmitter and receiver sections, each section with its own clock generator. table 49 shows the interface timing valu es. the number field in the ta ble refers to timing signals found in figure 37 and figure 38 . table 48. ecspi slave mo de timing parameters id parameter symbol min max unit cs1 ecspix_sclk cycle time?read ecspi_sclk cycle time?write t clk 15 43 ?ns cs2 ecspix_sclk high or low time?read ecspix_sclk high or low time?write t sw 7 21.5 ?ns cs4 ecspix_ss_b pulse width t cslh half ecspix_sclk period ? ns cs5 ecspix_ss_b lead time (cs setup time) t scs 5?ns cs6 ecspix_ss_b lag ti me (cs hold time) t hcs 5?ns cs7 ecspix_mosi setup time t smosi 4?ns cs8 ecspix_mosi hold time t hmosi 4?ns cs9 ecspix_miso propagation delay (c load =20pf) t pdmiso 419ns cs1 cs7 cs8 cs2 cs2 cs4 cs6 cs5 cs9 ecspix_sclk ecspix_ss_b ecspix_miso ecspix_mosi electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 71 table 49. enhanced serial audio interface (esai) timing no. characteristics 1,2 symbol expression 2 min max condition 3 unit 62 clock cycle 4 t ssicc 4 ? t c 4 ? t c 30.0 30.0 ? ? i ck i ck ns 63 clock high period: ? for internal clock ? for external clock ? ? 2 ? t c ?? 9.0 2 ? t c 6 15 ? ? ? ? ns 64 clock low period: ? for internal clock ? for external clock ? ? 2 ? t c ?? 9.0 2 ? t c 6 15 ? ? ? ? ns 65 esai_rx_clk rising edge to esai_rx_fs out (bl) high ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 66 esai_rx_clk rising edge to esai_rx_fs out (bl) low ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 67 esai_rx_clk rising edge to esai_rx_fs out (wr) high 5 ? ? ? ? ? ? 19.0 9.0 x ck i ck a ns 68 esai_rx_clk rising edge to esai_rx_fs out (wr) low 5 ? ? ? ? ? ? 19.0 9.0 x ck i ck a ns 69 esai_rx_clk rising edge to esai_rx_fs out (wl) high ? ? ? ? ? ? 16.0 6.0 x ck i ck a ns 70 esai_rx_clk rising edge to esai_rx_fs out (wl) low ? ? ? ? ? ? 17.0 7.0 x ck i ck a ns 71 data in setup time be fore esai_rx_clk (sck in synchronous mode) falling edge ? ? ? ? 12.0 19.0 ? ? x ck i ck ns 72 data in hold time after esai_rx_clk falling edge ? ? ? ? 3.5 9.0 ? ? x ck i ck ns 73 esai_rx_fs input (bl, wr) high before esai_rx_clk falling edge 5 ? ? ? ? 2.0 12.0 ? ? x ck i ck a ns 74 esai_rx_fs input (wl) high before esai_rx_clk falling edge ? ? ? ? 2.0 12.0 ? ? x ck i ck a ns 75 esai_rx_fs input hold time after esai_rx_clk falling edge ? ? ? ? 2.5 8.5 ? ? x ck i ck a ns 76 flags input setup befo re esai_rx_cl k falling edge ? ? ? ? 0.0 19.0 ? ? x ck i ck s ns 77 flags input hold time after esai_rx_clk falling edge ? ? ? ? 6.0 0.0 ? ? x ck i ck s ns 78 esai_tx_clk rising edge to esai_tx_fs out (bl) high ? ? ? ? ? ? 18.0 8.0 x ck i ck ns 79 esai_tx_clk rising edge to esai_tx_fs out (bl) low ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 80 esai_tx_clk rising edge to esai_tx_fs out (wr) high 5 ? ? ? ? ? ? 20.0 10.0 x ck i ck ns i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 72 nxp semiconductors electrical characteristics 81 esai_tx_clk rising edge to esai_tx_fs out (wr) low 5 ? ? ? ? ? ? 22.0 12.0 x ck i ck ns 82 esai_tx_clk rising edge to esai_tx_fs out (wl) high ? ? ? ? ? ? 19.0 9.0 x ck i ck ns 83 esai_tx_clk rising edge to esai_tx_fs out (wl) low ? ? ? ? ? ? 20.0 10.0 x ck i ck ns 84 esai_tx_clk rising edge to data out enable from high impedance ? ? ? ? ? ? 22.0 17.0 x ck i ck ns 85 esai_tx_clk rising e dge to transmitter #0 drive enable assertion ? ? ? ? ? ? 17.0 11.0 x ck i ck ns 86 esai_tx_clk rising edge to data out valid ? ? ? ? ? ? 18.0 13.0 x ck i ck ns 87 esai_tx_clk rising edge to data out high impedance 67 ? ? ? ? ? ? 21.0 16.0 x ck i ck ns 88 esai_tx_clk rising e dge to transmitter #0 drive enable deassertion 7 ??? ? 14.0 9.0 x ck i ck ns 89 esai_tx_fs input (bl, wr) setup time before esai_tx_clk falling edge 5 ? ? ? ? 2.0 18.0 ? ? x ck i ck ns 90 esai_tx_fs input (wl) se tup time before esai_tx_clk falling edge ? ? ? ? 2.0 18.0 ? ? x ck i ck ns 91 esai_tx_fs input hold time after esai_tx_clk falling edge ? ? ? ? 4.0 5.0 ? ? x ck i ck ns 92 esai_tx_fs input (wl) to data out enable from high impedance ???21.0?ns 93 esai_tx_fs input (wl) to tr ansmitter #0 drive enable assertion ???14.0?ns 94 flag output valid after esai_tx_clk rising edge ? ? ? ? 14.0 9.0 x ck i ck ns 95 esai_rx_hf_clk/esai_tx_hf _clk clock cycle ? 2 x t c 15 ? ? ns 96 esai_tx_hf_clk input rising edge to esai_tx_clk output ???18.0?ns 97 esai_rx_hf_clk input rising edge to esai_rx_clk output ???18.0?ns 1 i ck = internal clock x ck = external clock i ck a = internal clock, asynchronous mode (asynchronous implies that esai_tx_clk and esai_rx_clk are two different clocks) i ck s = internal clock, synchronous mode (synchronous implies th at esai_tx_clk a nd esai_rx_clk are the same clock) table 49. enhanced serial audio interface (esai) timing (continued) no. characteristics 1,2 symbol expression 2 min max condition 3 unit electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 73 figure 37. esai transmitter timing 2 bl = bit length wl = word length wr = word length relative 3 esai_tx_clk(sckt pin) = transmit clock esai_rx_clk(sckr pin) = receive clock esai_tx_fs(fst pin) = transmit frame sync esai_rx_fs(fsr pin) = receive frame sync esai_tx_hf_clk(hckt pin) = tr ansmit high frequency clock esai_rx_hf_clk(hckr pin) = re ceive high frequency clock 4 for the internal clock, the external clock cycle is defined by icyc and the esai control register. 5 the word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal waveform, but it spreads from one serial clock before the first bit clock (like the bit length frame sync signal), until the second-to-last bit clock of the first word in the frame. 6 periodically sampled and not 100% tested. esai_tx_clk (input/output) esai_tx_fs (bit) out esai_tx_fs (word) out data out esai_tx_fs (bit) in esai_tx_fs (word) in 62 64 78 79 82 83 87 86 86 84 91 89 90 91 63 last bit first bit i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 74 nxp semiconductors electrical characteristics figure 38. esai receiver timing figure 39. esai esai_tx_hf_clk timing esai_rx_clk (input/output) esai_rx_fs (bit) out esai_rx_fs (word) out data in esai_rx_fs (bit) in esai_rx_fs (word) in 62 64 65 69 70 72 71 75 73 74 75 63 66 first bit last bit esai_tx_hf_clk esai_tx_clk (output) 96 95 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 75 4.12.4 ultra high speed sd/sdio/ mmc host interface (usdhc) ac timing this section describes the electrical informat ion of the usdhc, which includes sd/emmc4.3 (single data rate) timing, emmc4.4/4.41 (dual date rate) timing and sdr104/50(sd3.0) timing. 4.12.4.1 sd/emmc4.3 (singl e data rate) ac timing figure 40 depicts the timing of sd/emmc4.3, and table 50 lists the sd/emmc4.3 ti ming characteristics. figure 40. sd/emmc4.3 timing table 50. sd/emmc4.3 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (low speed) f pp 1 0 400 khz clock frequency (sd/sdio full speed/high speed) f pp 2 0 25/50 mhz clock frequency (mmc full speed/high speed) f pp 3 0 20/52 mhz clock frequency (identification mode) f od 100 400 khz sd2 clock low time t wl 7?ns sd3 clock high time t wh 7?ns sd4 clock rise time t tlh ?3ns sd5 clock fall time t thl ?3ns usdhc output/card inputs sd_cmd , sdx_datax (reference to clk) sd6 usdhc output delay t od -6.6 3.6 ns sd1 sd3 sd5 sd4 sd7 sdx_clk sd2 sd8 sd6 output from usdhc to card input from card to usdhc sdx_data[7:0] sdx_data[7:0] i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 76 nxp semiconductors electrical characteristics 4.12.4.2 emmc4.4/4.41 (dua l data rate) ac timing figure 41 depicts the timi ng of emmc4.4/4.41. table 51 lists the emmc4.4/4.41 ti ming characteristics. be aware that only data is sampled on both e dges of the clock (not applicable to cmd). figure 41. emmc4.4/4.41 timing usdhc input/card outputs sd_cmd , sdx_datax (reference to clk) sd7 usdhc input setup time t isu 2.5 ? ns sd8 usdhc input hold time 4 t ih 1.5 ? ns 1 in low speed mode, card clock must be lower than 400 khz, voltage ranges from 2.7 to 3.6 v. 2 in normal (full) speed mode for sd/sdio card, clock frequency can be any value between 0 ? 25 mhz. in high-speed mode, clock frequency can be any value between 0 ? 50 mhz. 3 in normal (full) speed mode for mmc card, clock frequency can be any value between 0 ? 20 mhz. in high-speed mode, clock frequency can be any value between 0 ? 52 mhz. 4 to satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns. table 51. emmc4.4/4.41 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency (emmc4.4/4.41 ddr) f pp 052mhz sd1 clock frequency (sd3.0 ddr) f pp 050mhz usdhc output / card inputs sd_c md, sdx_datax (reference to clk) sd2 usdhc output delay t od 2.5 7.1 ns usdhc input / card outputs sd_cmd, sdx_datax (reference to clk) sd3 usdhc input setup time t isu 1.7 ? ns sd4 usdhc input hold time t ih 1.5 ? ns table 50. sd/emmc4.3 interface timing specification (continued) id parameter symbols min max unit sd1 sd2 sd3 output from esdhcv3 to card input from card to esdhcv3 sdx_data[7:0] sdx_clk sd4 sd2 ...... ...... sdx_data[7:0] electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 77 4.12.4.3 sdr50/sdr104 ac timing figure 42 depicts the timing of sdr50/sdr104, and table 52 lists the sdr50/sdr104 timing characteristics. figure 42. sdr50/sdr104 timing table 52. sdr50/sdr104 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5.0 ? ns sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd4 usdhc output delay t od ?3 1 ns usdhc output/card inputs sd_cmd, sdx_datax in sdr104 (reference to clk) sd5 usdhc output delay t od ?1.6 0.74 ns usdhc input/card outputs sd_cmd, sdx_datax in sdr50 (reference to clk) sd6 usdhc input setup time t isu 2.5 ? ns sd7 usdhc input hold time t ih 1.5 ? ns usdhc input/card outputs sd_cmd, sdx_datax in sdr104 (reference to clk) 1 1 data window in sdr104 mode is variable. sd8 card output data window t odw 0.5 x t clk ?ns 6 & . e l w r x w s x w i u r p x 6 ' + & w r f d u g e l w l q s x w i u r p f d u g w r x 6 ' + & 6 ' 6 ' 6 ' 6 ' 6 ' 6 ' 6 ' 6 ' i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 78 nxp semiconductors electrical characteristics 4.12.4.4 hs200 mode timing figure 43 depicts the timing of hs200 mode, and table 53 lists the hs200 timing characteristics. figure 43. hs200 mode timing 4.12.4.5 bus operation condition for 3.3 v and 1.8 v signaling signaling level of sd/emmc4.3 a nd emmc4.4/4.41 modes is 3.3 v. si gnaling level of sdr104/sdr50 mode is 1.8 v. the dc parameters for the nvcc _sd1 supply are identical to those shown in table 24, "single voltage gpio dc parameters," on page 38 . 4.12.5 ethernet controller (enet) ac electrical specifications the following timing specs are defined at the chip i/o pin and must be tr anslated appropria tely to arrive at timing specs/constraint s for the physical interface. table 53. hs200 interface timing specification id parameter symbols min max unit card input clock sd1 clock frequency period t clk 5.0 ? ns sd2 clock low time t cl 0.46 x t clk 0.54 x t clk ns sd3 clock high time t ch 0.46 x t clk 0.54 x t clk ns usdhc output/card inputs sd_cmd, sdx_datax in hs200 (reference to clk) sd5 usdhc output delay t od ?1.6 0.74 ns usdhc input/card outputs sd_cmd, sdx_datax in hs200 (reference to clk) 1 1 hs200 is for 8 bits while sdr104 is for 4 bits. sd8 card output data window t odw 0.5 x t clk ?ns 6 & . e l w r x w s x w i u r p x 6 ' + & w r h 0 0 & e l w l q s x w i u r p h 0 0 & w r x 6 ' + & 6 ' 6 ' 6 ' 6 ' 6 ' 6 ' electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 79 4.12.5.1 enet mii mode timing this subsection describes mii receive, transmit, as ynchronous inputs, and serial management signal timings. 4.12.5.1.1 mii receive si gnal timing (enet_rx_data 3,2,1,0, enet_rx_en, enet_rx_er, and enet_rx_clk) the receiver functions correctly up to an enet_rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. additionally, the processor clock frequency must exceed twice the enet_rx_clk frequency. figure 44 shows mii receive signal timings. table 54 describes the timing para meters (m1?m4) shown in the figure. figure 44. mii receive signal timing diagram 1 enet_rx_en, enet_rx_clk, and enet0_rxd0 have the same timing in 10 mbps 7-wire interface mode. 4.12.5.1.2 mii transmit signal timing (enet_tx_d ata3,2,1,0, enet_tx_en, enet_tx_er, and enet_tx_clk) the transmitter functions correctly up to an enet_tx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requi rement. additionally, the processo r clock frequency must exceed twice the enet_tx_clk frequency. table 54. mii receive signal timing id characteristic 1 min. max. unit m1 enet_rx_data3,2,1,0, en et_rx_en, enet_rx_er to enet_rx_clk setup 5? ns m2 enet_rx_clk to enet_rx_ data3,2,1,0, enet_rx_en, enet_rx_er hold 5? ns m3 enet_rx_clk pulse width hi gh 35% 65% enet_rx_clk period m4 enet_rx_clk pulse width low 35% 65% enet_rx_clk period enet_rx_clk (input) enet_rx_data3,2,1,0 m3 m4 m1 m2 enet_rx_er enet_rx_en (inputs) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 80 nxp semiconductors electrical characteristics figure 45 shows mii transm it signal timings. table 55 describes the timing pa rameters (m5?m8) shown in the figure. figure 45. mii transmit signal timing diagram 1 enet_tx_en, enet_tx_clk, and enet 0_txd0 have the same timing in 10-mbps 7-wire interface mode. 4.12.5.1.3 mii asynchronous inputs signal timing ( enet_crs and enet_col) figure 46 shows mii asynchronous input timings. table 56 describes the timing pa rameter (m9) shown in the figure. figure 46. mii async inputs timing diagram 1 enet_col has the same timing in 10-mbit 7-wire interface mode. table 55. mii transmit signal timing id characteristic 1 min. max. unit m5 enet_tx_clk to enet_tx_ data3,2,1,0, enet_tx_en, enet_tx_er invalid 5? ns m6 enet_tx_clk to enet_tx_ data3,2,1,0, enet_tx_en, enet_tx_er valid ?20 ns m7 enet_tx_clk pulse width hi gh 35% 65% enet_tx_clk period m8 enet_tx_clk pulse width low 35% 65% enet_tx_clk period table 56. mii asynchronous inputs signal timing id characteristic min. max. unit m9 1 enet_crs to enet_col minimum pulse width 1.5 ? enet_tx_clk period enet_tx_clk (input) enet_tx_data3,2,1,0 m7 m8 m5 m6 enet_tx_er enet_tx_en (outputs) enet_crs, enet_col m9 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 81 4.12.5.1.4 mii serial management ch annel timing (enet_mdio and enet_mdc) the mdc frequency is designed to be equal to or less than 2.5 mhz to be compatible with the ieee 802.3 mii specification. however the enet can function correctly with a maximum mdc frequency of 15 mhz. figure 47 shows mii asynchr onous input timings. table 57 describes the timing parameters (m10?m15) shown in the figure. figure 47. mii serial management channel timing diagram 4.12.5.2 rmii mode timing in rmii mode, enet_clk is used as the ref_cl k, which is a 50 mhz 50 ppm continuous reference clock. enet_rx_en is used as the rmii_crs_dv in rmii. other signals under rmii mode include enet_tx_en, enet_tx_data[1:0] , enet_rx_data[1:0] , and enet_rx_er. table 57. mii serial management channel timing id characteristic min. max. unit m10 enet_mdc falling edge to en et_mdio output invalid (min. propagation delay) 0? ns m11 enet_mdc falling edge to en et_mdio output valid (max. propagation delay) ?5 ns m12 enet_mdio (input) to enet_mdc rising edge setup 18 ? ns m13 enet_mdio (input) to enet_mdc rising edge hold 0 ? ns m14 enet_mdc pulse width high 40% 60% enet_mdc period m15 enet_mdc pulse width low 40% 60% enet_mdc period enet_mdc (output) enet_mdio (output) m14 m15 m10 m11 m12 m13 enet_mdio (input) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 82 nxp semiconductors electrical characteristics figure 48 shows rmii mode timings. table 58 describes the timing parame ters (m16?m21) shown in the figure. figure 48. rmii mode signal timing diagram 4.12.6 flexible controller area ne twork (flexcan) ac electrical specifications the flexible controller area network (flexcan) module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. the proces sor has two can modules available for systems design. tx a nd rx ports for both modules are multiplexed with other i/o pins. see the iomuxc chapter of the i.mx 6ull reference manual (imx6ullrm) to see wh ich pins expose tx and rx pins; these ports are named f lexcan_tx and flexcan_rx, respectively. table 58. rmii signal timing id characteristic min. max. unit m16 enet_clk pulse width high 35% 65% enet_clk period m17 enet_clk pulse width low 35% 65% enet_clk period m18 enet_clk to enet0_txd[1:0], enet_tx_data invalid 4 ? ns m19 enet_clk to enet0_txd[1: 0], enet_tx_data valid ? 13 ns m20 enet_rx_datad[1:0], enet_r x_en(enet_rx_en), enet_rx_er to enet_clk setup 2? ns m21 enet_clk to enet_rx_datad[ 1:0], enet_rx_en, enet_rx_er hold 2? ns enet_clk (input) enet_tx_en m16 m17 m18 m19 m20 m21 enet_rx_data[1:0] enet_tx_data (output) enet_rx_er enet_rx_en (input) electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 83 4.12.7 i 2 c bus characteristics the inter-integrated circuit (i2c) pr ovides functionality of a standard i2c master and slave. the i2c is designed to be compatible with the i2c bus speci fication, version 2.1, by phili ps semiconductor (now nxp semiconductors). 4.12.8 pulse width modulator (pwm) timing parameters this section describes the electrical information of the pwm. the pwm can be programmed to select one of three clock signals as its source frequency. the selected clock signal is passed through a prescaler before being input to the counter. the output is available at the pulse-width modulator output (pwmo) external pin. figure 49 depicts the timing of the pwm, and table 59 lists the pwm timing parameters. figure 49. pwm timing table 59. pwm output timing parameters id parameter min max unit pwm module clock frequency 0 66 mhz p1 pwm output pulse width high 15 ? ns p2 pwm output pulse width low 15 ? ns 0 7 - n ? / 5 4 0 0 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 84 nxp semiconductors electrical characteristics 4.12.9 lcd controller (lcdif) parameters figure 50 shows the lcdif timing and table 60 lists the timing parameters. figure 50. lcd timing 4.12.9.1 lcdif signal mapping table 61 lists the details about the mapping signals. table 60. lcd timing parameters id parameter symbol min max unit l1 lcd pixel clock frequency tclk(lcd) ? 150 mhz l2 lcd pixel clock high (falling edge capture) tclkh(lcd) 3 ? ns l3 lcd pixel clock low (rising edge capture) tclkl(lcd) 3 ? ns l4 lcd pixel clock high to data valid (falling edge capture) td(clkh-dv) -1 1 ns l5 lcd pixel clock low to data valid (rising edge capture) td(clkl-dv) -1 1 ns l6 lcd pixel clock high to control signal valid (falling edge capture) td(clkh-ctrlv) -1 1 ns l7 lcd pixel clock low to control signal valid (rising edge capture) td(clkl-ctrlv) -1 1 ns table 61. lcd timing parameters pin name 8-bit dotclk lcd if 16-bit dotclk lcd if 18-bit dotclk lcd if 24-bit dotclk lcd if 8-bit dvi lcd if lcd_rs ? ? ? ? ccir_clk lcd_vsync* (two options) lcd_vsync lcd_vsync lcd_vsync lcd_vsync ? lcd_hsync lcd_hsync lcd_hsync lcd_hsync lcd_hsync ? lcd_dotclk lcd_dotclk lcd_dotclk lcd_dotclk lcd_dotclk ? / / / / / & ' q b & / . i d o o l q j h g j h f d s w x u h / & ' q b & / . u l v l q j h g j h f d s w x u h / & ' q b ' $ 7 $ > @ / & ' q & r q w u r o 6 l j q d o v / / / electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 85 lcd_enable lcd_enable lcd_en able lcd_enable lcd_enable ? lcd_d23 ? ? ? r[7] ? lcd_d22 ? ? ? r[6] ? lcd_d21 ? ? ? r[5] ? lcd_d20 ? ? ? r[4] ? lcd_d19 ? ? ? r[3] ? lcd_d18 ? ? ? r[2] ? lcd_d17 ? ? r[5] r[1] ? lcd_d16 ? ? r[4] r[0] ? lcd_d15 / vsync* ? r[4] r[3] g[7] ? lcd_d14 / hsync** ? r[3] r[2] g[6] ? lcd_d13 / lcd_dotclk ** ? r21] r[1] g[5] ? lcd_d12 / enable** ? r[1] r[0] g[4] ? lcd_d11 ? r[0] g[5] g[3] ? lcd_d10 ? g[5] g[4] g[2] ? lcd_d9 ? g[4] g[3] g[1] ? lcd_d8 ? g[3] g[2] g[0] ? lcd_d8 ? g[3] g[2] g[0] ? lcd_d7 r[2] g[2] g[1] b[7] y/c[7] lcd_d6 r[1] g[1] g[0] b[6] y/c[6] lcd_d5 r[0] g[0] b[5] b[5] y/c[5] lcd_d4 g[2] b[4] b[4] b[4] y/c[4] lcd_d3 g[1] b[3] b[3] b[3] y/c[3] lcd_d2 g[0] b[2] b[2] b[2] y/c[2] lcd_d1 b[1] b[1] b[1] b[1] y/c[1] lcd_d0 b[0] b[0] b[0] b[0] y/c[0] lcd_reset lcd_reset lcd_re set lcd_reset lcd_reset ? lcd_busy / lcd_vsync lcd_busy (or optional lcd_vsync) lcd_busy (or optional lcd_vsync) lcd_busy (or optional lcd_vsync) lcd_busy (or optional lcd_vsync) ? table 61. lcd timing parameters (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 86 nxp semiconductors electrical characteristics 4.12.10 quad spi (qspi) timing parameters measurement conditions are with 35 pf load on sck and sio pins and input slew rate of 1 v/ns. 4.12.10.1 sdr mode figure 51. quadspi input/read timing (s dr mode with internal sampling) figure 52. quadspi input/read timing (sdr mode with loopback dqs sampling) note ? for internal sampling, the timing va lues assumes using sample point 0, that is quadspix_smpr[sdrsmp] = 0. table 62. quadspi input timing (sdr mode with internal sampling) symbol parameter value unit min max t is setup time for incoming data 8.67 ? ns t ih hold time requirement for incoming data 0 ? ns table 63. quadspi input/re ad timing (sdr mode with loopback dqs sampling) symbol parameter value unit min max t is setup time for incoming data 2 ? ns t ih hold time requirement for incoming data 1 ? ns 7 , 6 7 , + 7 , 6 7 , + 4 6 3 , [ b 6 & / . 4 6 3 , [ b ' $ 7 $ > @ 7 , 6 7 , 6 7 , + 7 , + 4 6 3 , [ b 6 & / . 4 6 3 , [ b ' $ 7 $ > @ 4 6 3 , [ b ' 4 6 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 87 ? for loopback dqs sampling, the data strobe is output to the dqs pad together with the serial clock. the data strobe is looped back from dqs pad and used to sample input data. figure 53. quadspi output/write timing (sdr mode) note t css and t csh are configured by the quadspi x_flshcr register, the default value of 3 are shown on the timing. please refer to the i.mx 6ull reference manual (imx6ullrm) for more details. table 64. quadspi output/write timing (sdr mode) symbol parameter value unit min max t dvo output data valid time ? 2 ns t dho output data hold time -0.5 ? ns t ck sck clock period 10 ? ns t css chip select output setup time 3 ? sck cycle(s) t csh chip select output ho ld time 3 ? sck cycle(s) 7 & 6 6 7 & . 7 & 6 + 7 ' 9 2 7 ' + 2 7 ' 9 2 7 ' + 2 4 6 3 , [ b 6 & / . 4 6 3 , [ b & 6 4 6 3 , [ b 6 , 2 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 88 nxp semiconductors electrical characteristics 4.12.10.2 ddr mode figure 54. quadspi input/read timing (ddr mode with internal sampling) figure 55. quadspi i nput/read timing (ddr mode wi th loopback dqs sampling) note ? for internal sampling, the timing va lues assumes using sample point 0, that is quadspix_smpr[sdrsmp] = 0. table 65. quadspi input/read timing (ddr mode with internal sampling) symbol parameter value unit min max t is setup time for incoming data 8.67 ? ns t ih hold time requirement for incoming data 0 ? ns table 66. quadspi input/read timing (ddr mode with loopback dqs sampling) symbol parameter value unit min max t is setup time for incoming data 2 ? ns t ih hold time requirement for incoming data 1 ? ns 7 , 6 7 , + 7 , 6 7 , + 4 6 3 , [ b 6 & / . 4 6 3 , [ b ' $ 7 $ > @ 7 , 6 7 , + 7 , 6 7 , + 4 6 3 , [ b 6 & / . 4 6 3 , [ b ' $ 7 $ > @ 4 6 3 , [ b ' 4 6 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 89 ? for loopback dqs sampling, the data strobe is output to the dqs pad together with the serial clock. the data strobe is looped back from dqs pad and used to sample input data. figure 56. quadspi output/write timing (ddr mode) note t css and t csh are configured by the quadspi x_flshcr register, the default value of 3 are shown on the timing. please refer to the i.mx 6ull reference manual (imx6ullrm) for more details. 4.12.11 sai/i2s switching specifications this section provides the ac timings for the sai in master (clocks driv en) and slave (clocks input) modes. all timings are given fo r non-inverted serial cl ock polarity (sai_tcr[tsc kp] = 0, sai_rcr[rsckp] = 0) and non-inverted fram e sync (sai_tcr[tfsi] = 0, sai_rcr[rfsi] = 0). if th e polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (sai_bclk) and/or the frame sync (s ai_fs) shown in the figures below. table 67. quadspi output/write timing (ddr mode) symbol parameter value unit min max t dvo output data valid time ? (0.25 x t sclk ) + 2 ns t dho output data hold time (0.25 x t sclk ) - 0.5 ? ns t ck sck clock period 20 ? ns t css chip select output setup time 3 ? sck cycle(s) t csh chip select output ho ld time 3 ? sck cycle(s) table 68. master mode sai timing num characteristic min max unit s1 sai_mclk cycle time 2 x t sys ?ns s2 sai_mclk pulse width high/low 40% 60% mclk period s3 sai_bclk cycle time 4 x t sys ?ns s4 sai_bclk pulse width high/low 40% 60% bclk period 7 & 6 6 7 & . 7 ' 9 2 7 ' + 2 7 ' 9 2 7 ' + 2 7 & 6 + 4 6 3 , [ b 6 & / . 4 6 3 , [ b & 6 4 6 3 , [ b 6 , 2 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 90 nxp semiconductors electrical characteristics figure 57. sai timing ? master modes s5 sai_bclk to sai_fs output valid ? 15 ns s6 sai_bclk to sai_fs output invalid 0 ? ns s7 sai_bclk to sai_txd valid ? 15 ns s8 sai_bclk to sai_txd invalid 0 ? ns s9 sai_rxd/sai_fs input se tup before sai_bclk 15 ? ns s10 sai_rxd/sai_fs input hold after sai_bclk 0 ? ns table 69. master mode sai timing num characteristic min max unit s11 sai_bclk cycle time (input) 4 x t sys ?ns s12 sai_bclk pulse width high/low (input) 40% 60% bclk period s13 sai_fs input setup before sai_bclk 10 ? ns s14 sai_fa input hold after sai_bclk 2 ? ns s15 sai_bclk to sai_txd/sai_fs output valid ? 20 ns s16 sai_bclk to sai_txd/sa i_fs output invalid 0 ? ns s17 sai_rxd setup before sai_bclk 10 ? ns s18 sai_rxd hold after sai_bclk 2 ? ns table 68. master mode sai timing (continued) num characteristic min max unit electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 91 figure 58. sai timing ? slave modes 4.12.12 scan jtag controller (sjc) timing parameters figure 59 depicts the sjc test clock input timing. figure 60 depicts the sjc boundary scan timing. figure 61 depicts the sjc test access port. signal parameters are listed in table 70 . figure 59. test clock input timing diagram jtag_tck (input) vm vm vih vil sj1 sj2 sj2 sj3 sj3 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 92 nxp semiconductors electrical characteristics figure 60. boundary scan (jtag) timing diagram jtag_tck (input) data inputs data outputs data outputs data outputs vih vil input data valid output data valid output data valid sj4 sj5 sj6 sj7 sj6 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 93 figure 61. test access port timing diagram figure 62. jtag_trst_b timing diagram table 70. jtag timing id parameter 1,2 all frequencies unit min max sj0 jtag_tck frequency of operation 1/(3?t dc ) 1 0.001 22 mhz sj1 jtag_tck cycle time in crystal mode 45 ? ns sj2 jtag_tck clock pulse width measured at v m 2 22.5 ? ns sj3 jtag_tck rise and fall times ? 3 ns sj4 boundary scan input data set-up time 5 ? ns sj5 boundary scan input data hold time 24 ? ns sj6 jtag_tck low to output data valid ? 40 ns sj7 jtag_tck low to output high impedance ? 40 ns jtag_tck (input) jtag_tdi (input) jtag_tdo (output) jtag_tdo (output) jtag_tdo (output) vih vil input data valid output data valid output data valid jtag_tms sj8 sj9 sj10 sj11 sj10 jtag_tck (input) jtag_trst_b (input) sj13 sj12 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 94 nxp semiconductors electrical characteristics 4.12.13 spdif timing parameters the sony/philips digital inte rface format (spdif) data is sent us ing the bi-phase marking code. when encoding, the spdif data signal is modulated by a clock that is twice the bit ra te of the data signal. table 71 , figure 63 , and figure 64 show spdif timing parameters for the sony/philips digital interconnect format (spdif), including the timing of the modulating rx clock (spdif_sr_clk) for spdif in rx mode and the timing of the modulating tx clock (spdif _st_clk) for spdif in tx mode. sj8 jtag_tms, jtag_tdi data set-up time 5 ? ns sj9 jtag_tms, jtag_tdi data hold time 25 ? ns sj10 jtag_tck low to jtag_tdo data valid ? 44 ns sj11 jtag_tck low to jtag_tdo high impedance ? 44 ns sj12 jtag_trst_b assert time 100 ? ns sj13 jtag_trst_b set-up time to jtag_tck low 40 ? ns 1 t dc = target frequency of sjc 2 v m = mid-point voltage table 71. spdif timing parameters characteristics symbol timing parameter range unit min max spdif_in skew: asynchronous inputs, no specs apply ?? 0.7ns spdif_out output (load = 50pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 24.2 31.3 ns spdif_out1 output (load = 30pf) ?skew ? transition rising ? transition falling ? ? ? ? ? ? 1.5 13.6 18.0 ns modulating rx clock (spdif_sr_clk) period srckp 40.0 ? ns spdif_sr_clk high period srckph 16.0 ? ns spdif_sr_clk low period srckpl 16.0 ? ns modulating tx clock (spdif_st_clk) period stclkp 40.0 ? ns spdif_st_clk high period stclkph 16.0 ? ns spdif_st_clk low pe riod stclkpl 16.0 ? ns table 70. jtag timing (continued) id parameter 1,2 all frequencies unit min max electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 95 figure 63. spdif_sr_clk timing diagram figure 64. spdif_st_clk timing diagram 4.12.14 uart i/o configurat ion and timing parameters 4.12.14.1 uart rs-232 serial mode timing the following sections describe the electrical information of the uart module in the rs-232 mode. 4.12.14.1.1 uart transmitter figure 65 depicts the transmit timing of uart in the rs- 232 serial mode, with 8 data bit/1 stop bit format. table 72 lists the uart rs-232 serial mode transmits timing characteristics. figure 65. uart rs-232 serial mode transmit timing diagram table 72. rs-232 serial mode transmit timing parameters id parameter symbol min max unit ua1 transmit bit time t tbit 1/f baud_rate 1 - t ref_clk 2 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). 1/f baud_rate + t ref_clk ? spdif_sr_clk (output) v m v m srckp srckph srckpl spdif_st_clk (input) v m v m stclkp stclkph stclkpl start bit bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_tx_data (output) bit 3 stop bit next start bit possible parity bit par bit ua1 ua1 ua1 ua1 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 96 nxp semiconductors electrical characteristics 4.12.14.1.2 uart receiver figure 66 depicts the rs-232 serial mode receives timing with 8 data bit/1 stop bit format. table 73 lists serial mode receive timing characteristics. figure 66. uart rs-232 serial mode receive timing diagram 4.12.14.1.3 uart irda mode timing the following subsections give the uart transmit and receive ti mings in irda mode. uart irda mode transmitter figure 67 depicts the uart irda mode transmit timing, with 8 data bit/1 stop bit format. table 74 lists the transmit timin g characteristics. figure 67. uart irda mode transmit timing diagram table 73. rs-232 serial mode receive timing parameters id parameter symbol min max unit ua2 receive bit time 1 1 the uart receiver can tolerate 1/(16 x f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 x f baud_rate ). t rbit 1/f baud_rate 2 - 1/(16 x f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16 x f baud_rate ) ? table 74. irda mode transmit timing parameters id parameter symbol min max unit ua3 transmit bit time in irda mode t tirbit 1/f baud_rate 1 - t ref_clk 2 1/f baud_rate + t ref_clk ? ua4 transmit ir pulse duration t tirpulse (3/16) x (1/f baud_rate ) - t ref_clk (3/16) x (1/f baud_rate ) + t ref_clk ? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 uartx_rx_data (output) bit 3 start bit stop bit next start bit possible parity bit par bit ua2 ua2 ua2 ua2 bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rgmii_txd (output) bit 3 start bit stop bit possible pa r i t y bit ua3 ua3 ua3 ua3 ua4 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 97 uart irda mode receiver figure 68 depicts the uart irda mode receive ti ming, with 8 data bit/1 stop bit format. table 75 lists the receive timing characteristics. figure 68. uart irda mode receive timing diagram 4.12.15 usb phy parameters this section describes the usb-otg phy parameters. the usb phy meets the electrical compliance requireme nts defined in the univer sal serial bus revision 2.0 otg with the following amendments. ? usb engineering change notice ? title: 5v short circuit withstand requirement change ? applies to: universal serial bus specification, revision 2.0 ? errata for usb revision 2.0 april 27, 2000 as of 12/7/2000 ? usb engineering change notice ? title: pull-up/pull-down resistors ? applies to: universal serial bus specification, revision 2.0 ? usb engineering change notice ? title: suspend current limit changes ? applies to: universal serial bus specification, revision 2.0 1 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 2 t ref_clk : the period of uart reference clock ref_clk ( ipg_perclk after rfdiv divider). table 75. irda mode receive timing parameters id parameter symbol min max unit ua5 receive bit time 1 in irda mode 1 the uart receiver can tolerate 1/(16 x f baud_rate ) tolerance in each bit. but accumulation tolerance in one frame must not exceed 3/(16 x f baud_rate ). t rirbit 1/f baud_rate 2 - 1/(16 x f baud_rate ) 2 f baud_rate : baud rate frequency. the maximum baud rate the uart can support is ( ipg_perclk frequency)/16. 1/f baud_rate + 1/(16 x f baud_rate ) ? ua6 receive ir pulse duration t rirpulse 1.41 ? s (5/16) x (1/f baud_rate )? bit 1 bit 2 bit 0 bit 4 bit 5 bit 6 bit 7 rgmii_rxd (input) bit 3 start bit stop bit possible pa r i t y bit ua5 ua5 ua5 ua5 ua6 i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 98 nxp semiconductors electrical characteristics ? usb engineering change notice ? title: usb 2.0 phase locked sofs ? applies to: universal serial bus specification, revision 2.0 ? on-the-go and embedded host supplement to the usb revision 2.0 specification ? revision 2.0 plus errata and ecn june 4, 2010 ? battery charging specificati on (available from usb-if) ? revision 1.2, december 7, 2010 ? portable device only 4.13 a/d converter the following subsections provide information about a/d converter. 4.13.1 12-bit adc electrical characteristics 4.13.1.1 12-bit adc operating conditions table 76. 12-bit adc operating conditions characteristic conditions symb min typ 1 max unit comment supply voltage absolute v ddad 3.0 - 3.6 v ? delta to vdd (vdd-vddad) 2 ? vddad -100 0 100 mv ? ground voltage delta to vss (vss-vssad) ? vssad -100 0 100 mv ? ref voltage high ? v refh 1.13 v ddad v ddad v ? ref voltage low ? v refl v ssad v ssad v ssad v ? input voltage ? v adin v refl ?v refh v ? input capacitance 8/10/12 bit modes c adin ?1.52 pf ? input resistance adlpc=0, adhsc=1 r adin ?57kohms ? adlpc=0, adhsc=0 ? 12.5 15 kohms ? adlpc=1, adhsc=0 ? 25 30 kohms ? analog source resistance 12 bit mode f adck = 40mhz adlsmp=0, adsts=10, adhsc=1 r as ??1 kohms t samp =150 ns r as depends on sample time setting (adlsmp, adsts) and ad c power mode (adhsc, adlpc). see charts for minimum sample time vs r as electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 99 figure 69. 12-bit adc input impedance equivalency diagram adc conversion clock frequency adlpc=0, adhsc=1 12 bit mode f adck 4 ? 40 mhz ? adlpc=0, adhsc=0 12 bit mode 4 ? 30 mhz ? adlpc=1, adhsc=0 12 bit mode 4 ? 20 mhz ? 1 typical values assume vddad = 3.0 v, temp = 25c, f adck =20 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2 dc potential differences table 76. 12-bit adc operat ing conditions (continued) characteristic conditions symb min typ 1 max unit comment i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 100 nxp semiconductors electrical characteristics 4.13.1.1.1 12-bit ad c characteristics table 77. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) characteristic conditions 1 symb min typ 2 max unit comment [l:] supply current adlpc=1, adhsc=0 i ddad ? 250 ? a adlsmp=0 adsts=10 adco=1 adlpc=0, adhsc=0 350 adlpc=0, adhsc=1 400 [l:] supply current stop, reset, module off i ddad ?0.010.8a ? adc asynchronous clock source adhsc=0 f adack ? 10 ? mhz t adack = 1/f adack adhsc=1 ? 20 ? sample cycles adlsmp=0, adsts=00 csamp ? 2 ? cycles ? adlsmp=0, adsts=01 4 adlsmp=0, adsts=10 6 adlsmp=0, adsts=11 8 adlsmp=1, adsts=00 12 adlsmp=1, adsts=01 16 adlsmp=1, adsts=10 20 adlsmp=1, adsts=11 24 electrical characteristics i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 101 conversion cycles adlsmp=0 adsts=00 cconv ? 28 ? cycles ? adlsmp=0 adsts=01 30 adlsmp=0 adsts=10 32 adlsmp=0 adsts=11 34 adlsmp=1 adsts=00 38 adlsmp=1 adsts=01 42 adlsmp=1 adsts=10 46 adlsmp=1, adsts=11 50 conversion time adlsmp=0 adsts=00 tconv ? 0.7 ? s fadc=40 mhz adlsmp=0 adsts=01 0.75 adlsmp=0 adsts=10 0.8 adlsmp=0 adsts=11 0.85 adlsmp=1 adsts=00 0.95 adlsmp=1 adsts=01 1.05 adlsmp=1 adsts=10 1.15 adlsmp=1, adsts=11 1.25 [p:][c:] total unadjusted error 12 bit mode tue ? 4.5 ? lsb 1 lsb = (v refh - v refl )/2 n ? 10 bit mode ? 2 ? 8 bit mode ? 1.5 ? [p:][c:] differential non-linearity 12 bit mode dnl ? 1 ? lsb ? 10bit mode ? 0.5 ? 8 bit mode ? 0.2 ? table 77. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions 1 symb min typ 2 max unit comment i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 102 nxp semiconductors electrical characteristics note the adc electrical spec would be met with the calibration enabled configuration. [p:][c:] integral non-linearity 12 bit mode inl ? 2.6 ? lsb ? 10bit mode ? 0.8 ? 8 bit mode ? 0.3 ? zero-scale error 12 bit mode e zs ? -0.3 ? lsb ? 10bit mode ? -0.15 ? 8 bit mode ? -0.15 ? full-scale error 12 bit mode e fs ? -2.5 ? lsb ? 10bit mode ? -0.6 ? 8 bit mode ? -0.3 ? [l:] effective number of bits 12 bit mode enob 10.1 10.7 ? bits ? [l:] signal to noise plus distortion see enob sinad sinad = 6.02 x enob + 1.76 db ? 1 all accuracy numbers assume the adc is calibrated with v refh =v ddad 2 typical values assume v ddad = 3.0 v, temp = 25c, f adck =20 mhz unless otherwise stated. typical values are for reference only and are not tested in production. table 77. 12-bit adc characteristics (v refh = v ddad , v refl = v ssad ) (continued) characteristic conditions 1 symb min typ 2 max unit comment boot mode configuration i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 103 5 boot mode configuration this section provides information on boot mode configuration pins allo cation and boot devices interfaces allocation. 5.1 boot mode configuration pins table 78 provides boot options, functionali ty, fuse values, and associated pi ns. several input pins are also sampled at reset and can be used to override fuse values, depending on the va lue of bt_fuse_sel fuse. the boot option pins are in effect when bt_fuse_sel fuse is ?0? (cleared, which is the case for an unblown fuse). for detailed boot m ode options configured by the boot m ode pins, see the i.mx 6ull fuse map document and the system boot chapter in i.mx 6ull reference manual (imx6ullrm) . table 78. fuses and associated pins used for boot pin direction at reset efuse name details boot_mode0 input with 100 k pull- down n/a boot mode selection boot_mode1 input with 100 k pull- down n/a boot mode selection i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 104 nxp semiconductors boot mode configuration 5.2 boot device interface allocation the following tables list the inte rfaces that can be used by the boot process in accordance with the specific boot mode configur ation. the tables also describe the in terface?s specific modes and iomuxc allocation, which are configured during boot when appropriate. lcd_data00 input with 100 k pull-down bt_cfg1[0] boot options, pin value overrides fuse settings for bt_fuse_sel = ?0?. signal configuration as fuse override input at power up. these are special i/o lines that control the boot up configuration during product development. in production, the boot configuration can be controlled by fuses. lcd_data01 input with 100 k pull-down bt_cfg1[1] lcd_data02 input with 100 k pull-down bt_cfg1[2] lcd_data03 input with 100 k pull-down bt_cfg1[3] lcd_data04 input with 100 k pull-down bt_cfg1[4] lcd_data05 input with 100 k pull-down bt_cfg1[5] lcd_data06 input with 100 k pull-down bt_cfg1[6] lcd_data07 input with 100 k pull-down bt_cfg1[7] lcd_data08 input with 100 k pull-down bt_cfg2[0] lcd_data09 input with 100 k pull-down bt_cfg2[1] lcd_data10 input with 100 k pull-down bt_cfg2[2] lcd_data11 input with 100 k pull-down bt_cfg2[3] lcd_data12 input with 100 k pull-down bt_cfg2[4] lcd_data13 input with 100 k pull-down bt_cfg2[5] lcd_data14 input with 100 k pull-down bt_cfg2[6] lcd_data15 input with 100 k pull-down bt_cfg2[7] lcd_data16 input with 100 k pull-down bt_cfg4[0] lcd_data17 input with 100 k pull-down bt_cfg4[1] lcd_data18 input with 100 k pull-down bt_cfg4[2] lcd_data19 input with 100 k pull-down bt_cfg4[3] lcd_data20 input with 100 k pull-down bt_cfg4[4] lcd_data21 input with 100 k pull-down bt_cfg4[5] lcd_data22 input with 100 k pull-down bt_cfg4[6] lcd_data23 input with 100 k pull-down bt_cfg4[7] table 79. qspi boot trough qspi ball name signal name mux mode common quad mode + port a dqs + port a cs1 + port b + port b dqs + port b cs1 nand_wp_b qspi.a_sclk alt2 yes yes nand_dqs qspi.a_ss0_b alt2 yes yes table 78. fuses and associated pins used for boot (continued) pin direction at reset efuse name details boot mode configuration i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 105 nand_ready_b qspi.a_data[0] alt2 yes yes nand_ce0_b qspi.a_data[1] alt2 yes yes nand_ce1_b qspi.a_data[2] alt2 yes yes nand_cle qspi.a_data[3] alt2 yes yes nand_data05 qspi.b_data[3] alt2 yes nand_data04 qspi.b_data[2] alt2 yes nand_data03 qspi.b_data[1] alt2 yes nand_data02 qspi.b_data[0] alt2 yes nand_we_b qspi.b_ss0_b alt2 yes nand_re_b qspi.b_sclk alt2 yes nand_data07 qspi. a_ss1_b alt2 yes nand_ale qspi.a_dqs alt2 yes nand_data00 qspi. b_ss1_b alt2 yes nand_data01 qspi.b_dqs alt2 yes table 80. spi boot through ecspi1 ball name signal name mux mode common boot_cfg4 [5:4]=00b boot_cfg4 [5:4]=01b boot_cfg4 [5:4]=10b boot_cfg4 [5:4]=11b csi_data07 ecspi1.miso alt 3 yes csi_data06 ecspi1.mosi alt 3 yes csi_data04 ecspi1.sclk alt 3 yes csi_data05 ecspi1.ss0 alt 3 yes lcd_data05 ecspi1.ss1 alt 8 yes lcd_data06 ecspi1.ss2 alt 8 yes lcd_data07 ecspi1.ss3 alt 8 yes table 81. spi boot through ecspi2 ball name signal name mux mode common boot_cfg 4[5:4]=00b boot_cfg4 [5:4]=01b boot_cfg4 [5:4]=10b boot_cfg4 [5:4]=11b csi_data03 ecspi2.miso alt 3 yes csi_data02 ecspi2.mosi alt 3 yes csi_data00 ecspi2.sclk alt 3 yes csi_data01 ecspi2.ss0 alt 3 yes lcd_hsync ecspi2.ss1 alt 8 yes table 79. qspi boot trough qspi (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 106 nxp semiconductors boot mode configuration lcd_vsync ecspi2.ss2 alt 8 yes lcd_reset ecspi2.ss3 alt 8 yes table 82. spi boot through ecspi3 ball name signal name mux mode common boot_cfg4 [5:4]=00b boot_cfg4[ 5:4]=01b boot_cfg4[ 5:4]=10b boot_cfg4 [5:4]=11b uart2_rts_b ecspi3.miso alt 8 yes uart2_cts_b ecspi3.mosi alt 8 yes uart2_rx_data ecspi3.sclk alt 8 yes uart2_tx_data ecspi3.ss0 alt 8 yes nand_ale ecspi3.ss1 alt 8 yes nand_re_b ecspi3.ss2 alt 8 yes nand_we_b ecspi3.ss3 alt 8 yes table 83. spi boot through ecspi4 ball name signal name mux mode common boot_cfg4 [5:4]=00b boot_cfg4[ 5:4]=01b boot_cfg4[ 5:4]=10b boot_cfg 4[5:4]=11b enet2_tx_clk ecspi4.miso alt 3 yes enet2_tx_en ecspi4.mosi alt 3 yes enet2_tx_data1 ecspi4.sclk alt 3 yes enet2_rx_er ecspi4.ss0 alt 3 yes nand_data01 ecspi4.ss1 alt 8 yes nand_data02 ecspi4.ss2 alt 8 yes nand_data03 ecspi4.ss3 alt 8 yes table 84. nand boot through gpmi ball name signal name mux mode common boot_cfg1[3:2]= 01b boot_cfg1[3:2]= 10b nand_cle rawnand.cle alt 0 yes nand_ale rawnand.ale alt 0 yes nand_wp_b rawnand.wp_b alt 0 yes nand_ready_b rawnand.ready_b alt 0 yes nand_ce0_b rawnand.ce0_b alt 0 yes nand_ce1_b rawnand.ce1_b alt 0 yes yes nand_re_b rawnand.re_b alt 0 yes table 81. spi boot through ecspi2 (continued) boot mode configuration i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 107 nand_we_b rawnand.we_b alt 0 yes nand_data00 rawnand.data00 alt 0 yes nand_data01 rawnand.data01 alt 0 yes nand_data02 rawnand.data02 alt 0 yes nand_data03 rawnand.data03 alt 0 yes nand_data04 rawnand.data04 alt 0 yes nand_data05 rawnand.data05 alt 0 yes nand_data06 rawnand.data06 alt 0 yes nand_data07 rawnand.data07 alt 0 yes nand_dqs rawnand.dqs alt 0 yes csi_mclk rawnand.ce2_b alt 2 yes csi_pixclk rawnand.ce3_b alt 2 yes table 85. sd/mmc boot through usdhc1 ball name signal name mux mode common 4-bit 8-bit boot_cfg1[1]=1 (sd power cycle) sdmmc mfg mode uart1_rts_b usdhc1.cd_b alt 2 yes sd1_clk usdhc1.clk alt 0 yes sd1_cmd usdhc1.cmd alt 0 yes sd1_data0 usdhc1.data0 alt 0 yes sd1_data1 usdhc1.data1 alt 0 yes yes sd1_data2 usdhc1.data2 alt 0 yes yes sd1_data3 usdhc1.data3 alt 0 yes nand_ready_b usdhc1.data4 alt 1 yes nand_ce0_b usdhc1.data5 alt 1 yes nand_ce1_b usdhc1.data6 alt 1 yes nand_cle usdhc1.data7 alt 1 yes gpio1_io09 gpio1_io09 1 1 the boot rom uses gpio1_io0 9 to implement sd1_reset_b. alt 5 yes gpio1_io05 usdhc1.vselect alt 4 yes table 84. nand boot through gpmi (continued) ball name signal name mux mode common boot_cfg1[3:2]= 01b boot_cfg1[3:2]= 10b i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 108 nxp semiconductors boot mode configuration table 86. sd/mmc boot through usdhc2 ball name signal name mux mode commo n 4-bit 8-bit boot_cfg1[1]=1 (sd power cycle) nand_re_b usdhc2.clk alt 1 yes nand_we_b usdhc2.cmd alt 1 yes nand_data00 usdhc2.data0 alt 1 yes nand_data01 usdhc2.data1 alt 1 yes yes nand_data02 usdhc2.data2 alt 1 yes yes nand_data03 usdhc2.data3 alt 1 yes nand_data04 usdhc2.data4 alt 1 yes nand_data05 usdhc2.data5 alt 1 yes nand_data06 usdhc2.data6 alt 1 yes nand_data07 usdhc2.data7 alt 1 yes nand_ale nand_ale 1 1 the boot rom uses nand_ale to implement sd2_reset_b. alt 5 yes gpio1_io08 usdhc2.vselect alt 4 yes table 87. nor/onenand boot through eim ball name signal name mux mode common adl16 non-mux ad16 mux csi_data00 weim.ad[0] alt 4 yes csi_data01 weim.ad[1] alt 4 yes csi_data02 weim.ad[2] alt 4 yes csi_data03 weim.ad[3] alt 4 yes csi_data04 weim.ad[4] alt 4 yes csi_data05 weim.ad[5] alt 4 yes csi_data06 weim.ad[6] alt 4 yes csi_data07 weim.ad[7] alt 4 yes nand_data00 weim.ad[8] alt 4 yes nand_data01 weim.ad[9] alt 4 yes nand_data02 weim.ad[10] alt 4 yes nand_data03 weim.ad[11] alt 4 yes nand_data04 weim.ad[12] alt 4 yes nand_data05 weim.ad[13] alt 4 yes nand_data06 weim.ad[14] alt 4 yes boot mode configuration i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 109 nand_data07 weim.ad[15] alt 4 yes nand_cle weim.addr[16] alt 4 yes yes nand_ale weim.addr[17] alt 4 yes yes nand_ce1_b weim.addr[18] alt 4 yes yes sd1_cmd weim.addr[19] alt 4 yes yes sd1_clk weim.addr[20] alt 4 yes yes sd1_data0 weim.addr[21] alt 4 yes yes sd1_data1 weim.addr[22] alt 4 yes yes sd1_data2 weim.addr[23] alt 4 yes yes sd1_data3 weim.addr[24] alt 4 yes yes enet2_rxer weim.addr[25] alt 4 yes yes enet2_crs_dv weim.a ddr[26] alt 4 yes yes csi_mclk weim.cs0_b alt 4 yes lcd_data08 weim.data[0] alt 4 yes lcd_data09 weim.data[1] alt 4 yes lcd_data10 weim.data[2] alt 4 yes lcd_data11 weim.data[3] alt 4 yes lcd_data12 weim.data[4] alt 4 yes lcd_data13 weim.data[5] alt 4 yes lcd_data14 weim.data[6] alt 4 yes lcd_data15 weim.data[7] alt 4 yes lcd_data16 weim.data[8] alt 4 yes lcd_data17 weim.data[9] alt 4 yes lcd_data18 weim.data[10] alt 4 yes lcd_data19 weim.data[11] alt 4 yes lcd_data20 weim.data[12] alt 4 yes lcd_data21 weim.data[13] alt 4 yes lcd_data22 weim.data[14] alt 4 yes lcd_data23 weim.data[15] alt 4 yes nand_re_b weim.eb_b[0] alt 4 yes yes nand_we_b weim.eb_b[1] alt 4 yes yes csi_hsync weim.lba_b alt 4 yes table 87. nor/onenand boot through eim (continued) ball name signal name mux mode common adl16 non-mux ad16 mux i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 110 nxp semiconductors boot mode configuration csi_pixclk weim.oe alt 4 yes csi_vsync weim.rw alt 4 yes table 88. serial download through uart1 ball name signal name mux mode common uart1_tx_data uart1.tx_data alt 0 yes uart1_rx_data uart1.rx_data alt 0 yes table 89. serial download through uart2 ball name signal name mux mode common uart2_tx_data uart2.tx_data alt 0 yes uart2_rx_data uart2.rx_data alt 0 yes table 87. nor/onenand boot through eim (continued) ball name signal name mux mode common adl16 non-mux ad16 mux package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 111 6 package information and contact assignments this section includes the contact assignment information and mechanical package drawing. 6.1 14 x 14 mm package information 6.1.1 14 x 14 mm, 0.8 mm pitch, ball matrix figure 70 shows the top, bottom, and side views of the 14 x 14 mm bga package. i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 112 nxp semiconductors package information and contact assignments figure 70. 14 x 14 mm bga, case x package top, bottom, and side views package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 113 6.1.2 14 x 14 mm supplies contact assi gnments and functional contact assignments table 90 shows the device connection list for groun d, sense, and reference contact signals. table 90. 14x14 mm supplies contact assignment supply rail name ball(s) position(s) remark adc_vrefh m13 ? dram_vref p4 ? gpanio r13 ? ngnd_kel0 m12 ? nvcc_csi f4 ? nvcc_dram g6, h6, j6, k6, l6, m6 ? nvcc_dram_2p5 n6 ? nvcc_enet f13 ? nvcc_gpio j13 ? nvcc_lcd e13 ? nvcc_nand e7 ? nvcc_pll p13 ? nvcc_sd1 c4 ? nvcc_uart h13 ? vdd_arm_cap g9, g10, g11, h11 ? vdd_high_cap r14, r15 ? vdd_high_in n13 ? vdd_snvs_cap n12 ? vdd_snvs_in p12 ? vdd_soc_cap g8, h8, j8, j11, k8, k11, l8, l9, l10, l11 ? vdd_soc_in h9, h10, j9, j10, k9, 10 ? vdd_usb_cap r12 ? vdda_adc_3p3 l13 ? vss a1, a17, c3, c7, c11, c15, e8, e11, f6, f7, f8, f9, f10,f11, f12, g3, g5, g7, g12, g15, h7, h12, j5, j7, j12, k7, k1 2, l3, l7, l12, m7, m8, m9, m10, m11, n3, n5, r3, r5, r7, r11, r16, r17, t14, u1, u14, u17 ? i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 114 nxp semiconductors package information and contact assignments table 91 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package. table 91. 14 x 14 mm functional contact assignments ball name 14x14 ball power group ball type out of reset condition default mode default function input/ output value boot_mode0 t10 vdd_snvs_in gpio alt5 gpio5_io10 input 100 k ? pull-down boot_mode1 u10 vdd_snvs_in gpio alt5 gpio5_io11 input 100 k ? pull-down ccm_clk1_n p16 vdd_high_cap ccm ? ccm_clk1_n ? ? ccm_clk1_p p17 vdd_high_cap ccm ? ccm_clk1_p ? ? ccm_pmic_stby_req u9 vdd_snvs_in ccm alt0 ccm_pmic_vstby_req output ? csi_data00 e4 nvcc_csi gpio alt5 gpio4_io21 input keeper csi_data01 e3 nvcc_csi gpio alt5 gpio4_io22 input keeper csi_data02 e2 nvcc_csi gpio alt5 gpio4_io23 input keeper csi_data03 e1 nvcc_csi gpio alt5 gpio4_io24 input keeper csi_data04 d4 nvcc_csi gpio alt5 gpio4_io25 input keeper csi_data05 d3 nvcc_csi gpio alt5 gpio4_io26 input keeper csi_data06 d2 nvcc_csi gpio alt5 gpio4_io27 input keeper csi_data07 d1 nvcc_csi gpio alt5 gpio4_io28 input keeper csi_hsync f3 nvcc_csi gpio alt5 gpio4_io20 input keeper csi_mclk f5 nvcc_csi gpio alt5 gpio4_io17 input keeper csi_pixclk e5 nvcc_csi gpio alt5 gpio4_io18 input keeper csi_vsync f2 nvcc_csi gpio alt5 gpio4_io19 input keeper dram_addr00 l5 nvcc_dram mmdc alt0 dram_addr00 output 100 k ? pull-up dram_addr01 h2 nvcc_dram ddr alt0 dram_addr01 output 100 k ? pull-up dram_addr02 k1 nvcc_dram ddr alt0 dram_addr02 output 100 k ? pull-up dram_addr03 m2 nvcc_dram ddr alt0 dram_addr03 output 100 k ? pull-up dram_addr04 k4 nvcc_dram ddr alt0 dram_addr04 output 100 k ? pull-up dram_addr05 l1 nvcc_dram ddr alt0 dram_addr05 output 100 k ? pull-up dram_addr06 g2 nvcc_dram ddr alt0 dram_addr06 output 100 k ? pull-up package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 115 dram_addr07 h4 nvcc_dram ddr alt0 dram_addr07 output 100 k ? pull-up dram_addr08 j4 nvcc_dram ddr alt0 dram_addr08 output 100 k ? pull-up dram_addr09 l2 nvcc_dram ddr alt0 dram_addr09 output 100 k ? pull-up dram_addr10 m4 nvcc_dram ddr alt0 dram_addr10 output 100 k ? pull-up dram_addr11 k3 nvcc_dram ddr alt0 dram_addr11 output 100 k ? pull-up dram_addr12 l4 nvcc_dram ddr alt0 dram_addr12 output 100 k ? pull-up dram_addr13 h3 nvcc_dram ddr alt0 dram_addr13 output 100 k ? pull-up dram_addr14 g1 nvcc_dram ddr alt0 dram_addr14 output 100 k ? pull-up dram_addr15 k5 nvcc_dram ddr alt0 dram_addr15 output 100 k ? pull-up dram_cas_b j2 nvcc_dram ddr alt0 dram_cas_b output 100 k ? pull-up dram_cs0_b n2 nvcc_dram ddr alt0 dram_cs0_b output 100 k ? pull-up dram_cs1_b h5 nvcc_dram ddr alt0 dram_cs1_b output 100 k ? pull-up dram_data00 t4 nvcc_dram ddr alt0 dram_data00 input 100 k ? pull-up dram_data01 u6 nvcc_dram ddr alt0 dram_data01 input 100 k ? pull-up dram_data02 t6 nvcc_dram ddr alt0 dram_data02 input 100 k ? pull-up dram_data03 u7 nvcc_dram ddr alt0 dram_data03 input 100 k ? pull-up dram_data04 u8 nvcc_dram ddr alt0 dram_data04 input 100 k ? pull-up dram_data05 t8 nvcc_dram ddr alt0 dram_data05 input 100 k ? pull-up dram_data06 t5 nvcc_dram ddr alt0 dram_data06 input 100 k ? pull-up dram_data07 u4 nvcc_dram ddr alt0 dram_data07 input 100 k ? pull-up dram_data08 u2 nvcc_dram ddr alt0 dram_data08 input 100 k ? pull-up table 91. 14 x 14 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 116 nxp semiconductors package information and contact assignments dram_data09 u3 nvcc_dram ddr alt0 dram_data09 input 100 k ? pull-up dram_data10 u5 nvcc_dram ddr alt0 dram_data10 input 100 k ? pull-up dram_data11 r4 nvcc_dram ddr alt0 dram_data11 input 100 k ? pull-up dram_data12 p5 nvcc_dram ddr alt0 dram_data12 input 100 k ? pull-up dram_data13 p3 nvcc_dram ddr alt0 dram_data13 input 100 k ? pull-up dram_data14 r2 nvcc_dram ddr alt0 dram_data14 input 100 k ? pull-up dram_data15 r1 nvcc_dram ddr alt0 dram_data15 input 100 k ? pull-up dram_dqm0 t7 nvcc_dram ddr alt0 dram_dqm0 output 100 k ? pull-up dram_dqm1 t3 nvcc_dram ddr alt0 dram_dqm1 output 100 k ? pull-up dram_odt0 n1 nvcc_dram ddr alt0 dram_odt0 output 100 k ? pull-down dram_odt1 f1 nvcc_dram ddr alt0 dram_odt1 output 100 k ? pull-down dram_ras_b m5 nvcc_dram ddr alt0 dram_ras_b output 100 k ? pull-up dram_reset g4 nvcc_dram ddr alt0 dram_reset output 100 k ? pull-down dram_sdba0 m1 nvcc_dram ddr alt0 dram_sdba0 output 100 k ? pull-up dram_sdba1 h1 nvcc_dram ddr alt0 dram_sdba1 output 100 k ? pull-up dram_sdba2 k2 nvcc_dram ddr alt0 dram_sdba2 output 100 k ? pull-up dram_sdcke0 m3 nvcc_dram ddr alt0 dram_sdcke0 output 100 k ? pull-down dram_sdcke1 j3 nvcc_dram ddr alt0 dram_sdcke1 output 100 k ? pull-down dram_sdclk0_n p2 nvcc_dram ddrcl k alt0 dram_sdclk0_n input 100 k ? pull-up dram_sdclk0_p p1 nvcc_dram ddrcl k alt0 dram_sdclk0_p input 100 k ? pull-up dram_sdqs0_n p7 nvcc_dram ddrcl k alt0 dram_sdqs0_n input 100 k ? pull-down table 91. 14 x 14 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 117 dram_sdqs0_p p6 nvcc_dram ddrcl k alt0 dram_sdqs0_p input 100 k ? pull-down dram_sdqs1_n t2 nvcc_dram ddrcl k alt0 dram_sdqs1_n input 100 k ? pull-down dram_sdqs1_p t1 nvcc_dram ddrcl k alt0 dram_sdqs1_p input 100 k ? pull-down dram_sdwe_b j1 nvcc_dram ddr alt0 dram_sdwe_b output 100 k ? pull-up dram_zqpad n4 nvcc_dram gpio ? dram_zqpad input keeper enet1_rx_data0 f16 nvcc_enet gpio alt5 gpio2_io0 input keeper enet1_rx_data1 e17 nvcc_enet gpio alt5 gpio2_io1 input keeper enet1_rx_en e16 nvcc_enet gp io alt5 gpio2_io2 input keeper enet1_rx_er d15 nvcc_enet gpio alt5 gpio2_io7 input keeper enet1_tx_clk f14 nvcc_enet gp io alt5 gpio2_io6 input keeper enet1_tx_data0 e15 nvcc_enet gp io alt5 gpio2_io3 input keeper enet1_tx_data1 e14 nvcc_enet gp io alt5 gpio2_io4 input keeper enet1_tx_en f15 nvcc_enet gp io alt5 gpio2_io5 input keeper enet2_rx_data0 c17 nvcc_enet gpio alt5 gpio2_io8 input keeper enet2_rx_data1 c16 nvcc_enet gpio alt5 gpio2_io9 input keeper enet2_rx_en b17 nvcc_enet gpio alt5 gpio2_io10 input keeper enet2_rx_er d16 nvcc_enet gpio alt5 gpio2_io15 input keeper enet2_tx_clk d17 nvcc_enet gpio alt5 gpio2_io14 input keeper enet2_tx_data0 a15 nvcc_enet gpio alt5 gpio2_io11 input keeper enet2_tx_data1 a16 nvcc_enet gpio alt5 gpio2_io12 input keeper enet2_tx_en b15 nvcc_enet gpio alt5 gpio2_io13 input keeper gpio1_io00 k13 nvcc_gpio gpio alt5 gpio1_io00 input keeper gpio1_io01 l15 nvcc_gpio gpio alt5 gpio1_io01 input keeper gpio1_io02 l14 nvcc_gpio gpio alt5 gpio1_io02 input keeper gpio1_io03 l17 nvcc_gpio gpio alt5 gpio1_io03 input keeper gpio1_io04 m16 nvcc_gpio gpio alt5 gpio1_io04 input keeper gpio1_io05 m17 nvcc_gpio gpio alt5 gpio1_io05 input keeper gpio1_io06 k17 nvcc_gpio gpio alt5 gpio1_io06 input keeper gpio1_io07 l16 nvcc_gpio gpio alt5 gpio1_io07 input keeper gpio1_io08 n17 nvcc_gpio gpio alt5 gpio1_io08 input keeper gpio1_io09 m15 nvcc_gpio gpio alt5 gpio1_io09 input keeper table 91. 14 x 14 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 118 nxp semiconductors package information and contact assignments jtag_mod p15 nvcc_gpio sjc alt0 sjc_mod input 100 k ? pull-up jtag_tck m14 nvcc_gpio sjc alt0 sjc_tck input 47 k ? pull-up jtag_tdi n16 nvcc_gpio sjc alt0 sjc_tdi input 47 k ? pull-up jtag_tdo n15 nvcc_gpio sjc alt0 sjc_tdo output keeper jtag_tms p14 nvcc_gpio sjc alt0 sjc_tms input 47 k ? pull-up jtag_trst_b n14 nvcc_gpio sjc alt0 sjc_trstb input 47 k ? pull-up lcd_clk a8 nvcc_lcd gpio alt5 gpio3_io0 input keeper lcd_data00 b9 nvcc_lcd gpio alt5 gpio3_io5 input keeper lcd_data01 a9 nvcc_lcd gpio alt5 gpio3_io6 input keeper lcd_data02 e10 nvcc_lcd gpio alt5 gpio3_io7 input keeper lcd_data03 d10 nvcc_lcd gpio alt5 gpio3_io8 input keeper lcd_data04 c10 nvcc_lcd gpio alt5 gpio3_io9 input keeper lcd_data05 b10 nvcc_lcd gpio alt5 gpio3_io10 input keeper lcd_data06 a10 nvcc_lcd gpio alt5 gpio3_io11 input keeper lcd_data07 d11 nvcc_lcd gpio alt5 gpio3_io12 input keeper lcd_data08 b11 nvcc_lcd gpio alt5 gpio3_io13 input keeper lcd_data09 a11 nvcc_lcd gpio alt5 gpio3_io14 input keeper lcd_data10 e12 nvcc_lcd gpio alt5 gpio3_io15 input keeper lcd_data11 d12 nvcc_lcd gpio alt5 gpio3_io16 input keeper lcd_data12 c12 nvcc_lcd gpio alt5 gpio3_io17 input keeper lcd_data13 b12 nvcc_lcd gpio alt5 gpio3_io18 input keeper lcd_data14 a12 nvcc_lcd gpio alt5 gpio3_io19 input keeper lcd_data15 d13 nvcc_lcd gpio alt5 gpio3_io20 input keeper lcd_data16 c13 nvcc_lcd gpio alt5 gpio3_io21 input keeper lcd_data17 b13 nvcc_lcd gpio alt5 gpio3_io22 input keeper lcd_data18 a13 nvcc_lcd gpio alt5 gpio3_io23 input keeper lcd_data19 d14 nvcc_lcd gpio alt5 gpio3_io24 input keeper lcd_data20 c14 nvcc_lcd gpio alt5 gpio3_io25 input keeper lcd_data21 b14 nvcc_lcd gpio alt5 gpio3_io26 input keeper lcd_data22 a14 nvcc_lcd gpio alt5 gpio3_io27 input keeper lcd_data23 b16 nvcc_lcd gpio alt5 gpio3_io28 input keeper table 91. 14 x 14 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 119 lcd_enable b8 nvcc_lcd gpio alt5 gpio3_io1 input keeper lcd_hsync d9 nvcc_lcd gpio alt5 gpio3_io2 input keeper lcd_reset e9 nvcc_lcd gpio a lt5 gpio3_io4 input keeper lcd_vsync c9 nvcc_lcd gpio a lt5 gpio3_io3 input keeper nand_ale b4 nvcc_nand gpio alt5 gpio4_io10 input keeper nand_ce0_b c5 nvcc_nand gpio alt5 gpio4_io13 input keeper nand_ce1_b b5 nvcc_nand gpio alt5 gpio4_io14 input keeper nand_cle a4 nvcc_nand gpio alt5 gpio4_io15 input keeper nand_data00 d7 nvcc_nand gpio alt5 gpio4_io2 input keeper nand_data01 b7 nvcc_nand gpio alt5 gpio4_io3 input keeper nand_data02 a7 nvcc_nand gpio alt5 gpio4_io4 input keeper nand_data03 d6 nvcc_nand gpio alt5 gpio4_io5 input keeper nand_data04 c6 nvcc_nand gpio alt5 gpio4_io6 input keeper nand_data05 b6 nvcc_nand gpio alt5 gpio4_io7 input keeper nand_data06 a6 nvcc_nand gpio alt5 gpio4_io8 input keeper nand_data07 a5 nvcc_nand gpio alt5 gpio4_io9 input keeper nand_dqs e6 nvcc_nand gpio alt5 gpio4_io16 input keeper nand_re_b d8 nvcc_nand gpio alt5 gpio4_io0 input keeper nand_ready_b a3 nvcc_nand gpio alt5 gpio4_io12 input keeper nand_we_b c8 nvcc_nand gpio alt5 gpio4_io1 input keeper nand_wp_b d5 nvcc_nand gpio alt5 gpio4_io11 input keeper onoff r8 vdd_snvs_in src alt0 src_reset_b input 100 k ? pull-up por_b p8 vdd_snvs_in src alt0 src_por_b input 100 k ? pull-up rtc_xtali t11 vdd_snvs_cap analo g ? rtc_xtali ? ? rtc_xtalo u11 vdd_snvs_cap analo g ?rtc_xtalo ?? sd1_clk c1 nvcc_sd gpio alt5 gpio2_io17 input keeper sd1_cmd c2 nvcc_sd gpio alt5 gpio2_io16 input keeper sd1_data0 b3 nvcc_sd gpio alt5 gpio2_io18 input keeper sd1_data1 b2 nvcc_sd gpio alt5 gpio2_io19 input keeper sd1_data2 b1 nvcc_sd gpio alt5 gpio2_io20 input keeper sd1_data3 a2 nvcc_sd gpio alt5 gpio2_io21 input keeper table 91. 14 x 14 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 120 nxp semiconductors package information and contact assignments snvs_pmic_on_req t9 vdd_snvs_in gpio alt0 snvs_pmic_on_req output 100 k ? pull-up snvs_tamper0 r10 vdd_snvs_in gpio alt5 gpio5_io00/snvs_tampe r0 1 input keeper/n ot connecte d 1,2 snvs_tamper1 r9 vdd_snvs_in gpio alt5 gpio5_io01/snvs_tampe r1 1 input keeper/n ot connecte d 1,2 snvs_tamper2 p11 vdd_snvs_in gpio alt5 gpio5_io02/snvs_tampe r2 1 input keeper/n ot connecte d 1,2 snvs_tamper3 p10 vdd_snvs_in gpio alt5 gpio5_io03/snvs_tampe r3 1 input keeper/n ot connecte d 1,2 snvs_tamper4 p9 vdd_snvs_in gpio alt5 gpio5_io04/snvs_tampe r4 1 input keeper/n ot connecte d 1,2 snvs_tamper5 n8 vdd_snvs_in gpio alt5 gpio5_io05/snvs_tampe r5 1 input keeper/n ot connecte d 1,2 snvs_tamper6 n11 vdd_snvs_in gpio alt5 gpio5_io06/snvs_tampe r6 1 input keeper/n ot connecte d 1,2 snvs_tamper7 n10 vdd_snvs_in gpio alt5 gpio5_io07/snvs_tampe r7 1 input keeper/n ot connecte d 1,2 snvs_tamper8 n9 vdd_snvs_in gpio alt5 gpio5_io08/snvs_tampe r8 1 input keeper/n ot connecte d 1,2 snvs_tamper9 r6 vdd_snvs_in gpio alt5 gpio5_io09/snvs_tampe r9 1 input keeper/n ot connecte d 1,2 test_mode n7 vdd_snvs_in tcu alt 0 tcu_test_mode input keeper uart1_cts_b k15 nvcc_uart gpio alt5 gpio1_io18 input keeper uart1_rts_b j14 nvcc_uart gpio alt5 gpio1_io19 input keeper uart1_rx_data k16 nvcc_uart gpio alt5 gpio1_io17 input keeper table 91. 14 x 14 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 121 uart1_tx_data k14 nvcc_uart gpio alt5 gpio1_io16 input keeper uart2_cts_b j15 nvcc_uart gpio alt5 gpio1_io22 input keeper uart2_rts_b h14 nvcc_uart gpio alt5 gpio1_io23 input keeper uart2_rx_data j16 nvcc_uart gpio alt5 gpio1_io21 input keeper uart2_tx_data j17 nvcc_uart gpio alt5 gpio1_io20 input keeper uart3_cts_b h15 nvcc_uart gpio alt5 gpio1_io26 input keeper uart3_rts_b g14 nvcc_uart gpio alt5 gpio1_io27 input keeper uart3_rx_data h16 nvcc_uart gpio alt5 gpio1_io25 input keeper uart3_tx_data h17 nvcc_uart gpio alt5 gpio1_io24 input keeper uart4_rx_data g16 nvcc_uart gpio alt5 gpio1_io29 input keeper uart4_tx_data g17 nvcc_uart gpio alt5 gpio1_io28 input keeper uart5_rx_data g13 nvcc_uart gpio alt5 gpio1_io31 input keeper uart5_tx_data f17 nvcc_uart gpio alt5 gpio1_io30 input keeper usb_otg1_chd_b u16 open drain gpio ? usb_otg1_chd_b ? ? usb_otg1_dn t15 vdd_usb_cap analo g ? usb_otg1_dn ? ? usb_otg1_dp u15 vdd_usb_cap analo g ? usb_otg1_dp ? ? usb_otg1_vbus t12 usb_vbus vbus powe r ? usb_otg1_vbus ? ? usb_otg2_dn t13 vdd_usb_cap analo g ? usb_otg2_dn ? ? usb_otg2_dp u13 vdd_usb_cap analo g ? usb_otg2_dp ? ? usb_otg2_vbus u12 usb_vbus vbus powe r ? usb_otg2_vbus ? ? xtali t16 nvcc_pll analo g ?xtali ?? xtalo t17 nvcc_pll analo g ?xtalo ?? 1 snvs_tamper0 to snvs_tamper9 can be configured as gpio or ta mper detection pin, it is de pending on the fuse setting tamper_pin_disable[1:0]. when the pad is configured as gpio, the value is keeper out of reset. 2 snvs_tamper0 to snvs_tamper9 is input unconnected in the following conditions. ?snvs low power mode when configured as gpio ?tamper functions are not used when configured as tamper detection pins it is required to connect external 1m ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two conditions above. table 91. 14 x 14 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 122 nxp semiconductors package information and contact assignments 6.1.3 14 x 14 mm, 0.8 mm pitch, ball map table 92 shows the 14 x 14 mm, 0.8 mm pitch ball map for the i.mx 6ull. table 92. 14 x 14 mm, 0.8 mm pitch, ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a vss sd1_data3 nand_ready_b nand_cle nand_data07 nand_data06 nand_data02 lcd_clk lcd_data01 lcd_data06 lcd_data09 lcd_data14 lcd_data18 lcd_data22 enet2_tx_data0 enet2_tx_data1 vss a b sd1_data2 sd1_data1 sd1_data0 nand_ale nand_ce1_b nand_data05 nand_data01 lcd_enable lcd_data00 lcd_data05 lcd_data08 lcd_data13 lcd_data17 lcd_data21 enet2_tx_en lcd_data23 enet2_rx_en b c sd1_clk sd1_cmd vss nvcc_sd1 nand_ce0_b nand_data04 vss nand_we_b lcd_vsync lcd_data04 vss lcd_data12 lcd_data16 lcd_data20 vss enet2_rx_data1 enet2_rx_data0 c d csi_data07 csi_data06 csi_data05 csi_data04 nand_wp_b nand_data03 nand_data00 nand_re_b lcd_hsync lcd_data03 lcd_data07 lcd_data11 lcd_data15 lcd_data19 enet1_rx_er enet2_rx_er enet2_tx_clk d e csi_data03 csi_data02 csi_data01 csi_data00 csi_pixclk nand_dqs nvcc_nand vss lcd_reset lcd_data02 vss lcd_data10 nvcc_lcd enet1_tx_data1 enet1_tx_data0 enet1_rx_en enet1_rx_data1 e f dram_odt1 csi_vsync csi_hsync nvcc_csi csi_mclk vss vss vss vss vss vss vss nvcc_enet enet1_tx_clk enet1_tx_en enet1_rx_data0 uart5_tx_data f g dram_addr14 dram_addr06 vss dram_reset vss nvcc_dram vss vdd_soc_cap vdd_arm_cap vdd_arm_cap vdd_arm_cap vss uart5_rx_data uart3_rts_b vss uart4_rx_data uart4_tx_data g package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 123 h dram_sdba1 dram_addr01 dram_addr13 dram_addr07 dram_cs1_b nvcc_dram vss vdd_soc_cap vdd_soc_in vdd_soc_in vdd_arm_cap vss nvcc_uart uart2_rts_b uart3_cts_b uart3_rx_data uart3_tx_data h j dram_sdwe_b dram_cas_b dram_sdcke1 dram_addr08 vss nvcc_dram vss vdd_soc_cap vdd_soc_in vdd_soc_in vdd_soc_cap vss nvcc_gpio uart1_rts_b uart2_cts_b uart2_rx_data uart2_tx_data j k dram_addr02 dram_sdba2 dram_addr11 dram_addr04 dram_addr15 nvcc_dram vss vdd_soc_cap vdd_soc_in vdd_soc_in vdd_soc_cap vss gpio1_io00 uart1_tx_data uart1_cts_b uart1_rx_data gpio1_io06 k l dram_addr05 dram_addr09 vss dram_addr12 dram_addr00 nvcc_dram vss vdd_soc_cap vdd_soc_cap vdd_soc_cap vdd_soc_cap vss vdda_adc_3p3 gpio1_io02 gpio1_io01 gpio1_io07 gpio1_io03 l m dram_sdba0 dram_addr03 dram_sdcke0 dram_addr10 dram_ras_b nvcc_dram vss vss vss vss vss ngnd_kel0 adc_vrefh jtag_tck gpio1_io09 gpio1_io04 gpio1_io05 m n dram_odt0 dram_cs0_b vss dram_zqpad vss nvcc_dram_2p5 test_mode snvs_tamper5 snvs_tamper8 snvs_tamper7 snvs_tamper6 vdd_snvs_cap vdd_high_in jtag_trst_b jtag_tdo jtag_tdi gpio1_io08 n p dram_sdclk0_p dram_sdclk0_n dram_data13 dram_vref dram_data12 dram_sdqs0_p dram_sdqs0_n por_b snvs_tamper4 snvs_tamper3 snvs_tamper2 vdd_snvs_in nvcc_pll jtag_tms jtag_mod ccm_clk1_n ccm_clk1_p p table 92. 14 x 14 mm, 0.8 mm pitch, ball map (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 124 nxp semiconductors package information and contact assignments 6.2 9 x 9 mm package information 6.2.1 9 x 9 mm, 0.5 mm pitch, ball matrix figure 71 shows the top, bottom, and side vi ews of the 9 x 9 mm bga package. r dram_data15 dram_data14 vss dram_data11 vss snvs_tamper9 vss onoff snvs_tamper1 snvs_tamper0 vss vdd_usb_cap gpanaio vdd_high_cap vdd_high_cap vss vss r t dram_sdqs1_p dram_sdqs1_n dram_dqm1 dram_data00 dram_data06 dram_data02 dram_dqm0 dram_data05 snvs_pmic_on_req boot_mode0 rtc_xtali usb_otg1_vbus usb_otg2_dn vss usb_otg1_dn xtali xtalo t u vss dram_data08 dram_data09 dram_data07 dram_data10 dram_data01 dram_data03 dram_data04 ccm_pmic_stby_req boot_mode1 rtc_xtalo usb_otg2_vbus usb_otg2_dp vss usb_otg1_dp usb_otg1_chd_b vss u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 table 92. 14 x 14 mm, 0.8 mm pitch, ball map (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 125 figure 71. 9 x 9 mm bga, case x packa ge top, bottom, and side views i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 126 nxp semiconductors package information and contact assignments 6.2.2 9 x 9 mm supplies contact assignments and functional contact assignments table 93 shows the device connection list for groun d, sense, and reference contact signals. table 93. 9 x 9 mm supplies contact assignment supply rail name ball(s) position(s) remark adc_vrefh n13 ? dram_vref t1 ? gpanaio t11 ? ngnd_kel0 m10 ? nvcc_csi e5 ? nvcc_dram g5, l5, m5, n6 ? nvcc_dram_2p5 k6 ? nvcc_enet g13 ? nvcc_gpio m13 ? nvcc_lcd e13 ? nvcc_nand e11 ? nvcc_pll t13 ? nvcc_sd1 e7 ? nvcc_uart l13 ? vdd_arm_cap g9, g10, g11, h9, h10, h11 ? vdd_high_cap u11 ? vdd_high_in u15 ? vdd_snvs_cap n12 ? vdd_snvs_in p12 ? vdd_soc_cap g7, g8, h7, h8, j7, j8, k7, k8, l7, l8 ? vdd_soc_in j9, j10, j11, k9, k10, k11, l9, l10, l11 ? vdd_usb_cap n11 ? vdda_adc_3p3 t17 ? vss a2, a7, a12, a17, b1, c15, f1, f3, f8, f10, f17, h6, h12, j3, j15, k12, m1, m3, m8, m17, r3, r9, r12, r15, u1, u6, u13, u17 ? package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 127 table 94 shows an alpha-sorted list of functional co ntact assignments for the 9 x 9 mm package. table 94. 9 x 9 mm functional contact assignments ball name 9x9 ball power group ball type out of reset condition default mode default function input/ output value boot_mode0 t8 vdd_snvs_in gpio alt5 gpio5_io10 input 100 k ? pull-down boot_mode1 u8 vdd_snvs_in gpio alt5 gpio5_io11 input 100 k ? pull-down ccm_clk1_n u16 vdd_high_cap lvds ? ccm_clk1_n ? ? ccm_clk1_p t16 vdd_high_cap lvds ? ccm_clk1_p ? ? ccm_pmic_stby_req u7 vdd_snvs_in gp io alt0 ccm_pmic_vstby_req output ? csi_data00 c3 nvcc_csi gpio alt5 gpio4_io21 input keeper csi_data01 d4 nvcc_csi gpio alt5 gpio4_io22 input keeper csi_data02 b2 nvcc_csi gpio alt5 gpio4_io23 input keeper csi_data03 d1 nvcc_csi gpio alt5 gpio4_io24 input keeper csi_data04 c4 nvcc_csi gpio alt5 gpio4_io25 input keeper csi_data05 b3 nvcc_csi gpio alt5 gpio4_io26 input keeper csi_data06 a3 nvcc_csi gpio alt5 gpio4_io27 input keeper csi_data07 c2 nvcc_csi gpio alt5 gpio4_io28 input keeper csi_hsync d2 nvcc_csi gpio alt5 gpio4_io20 input keeper csi_mclk c1 nvcc_csi gpio alt5 gpio4_io17 input keeper csi_pixclk d5 nvcc_csi gpio alt5 gpio4_io18 input keeper csi_vsync d3 nvcc_csi gpio alt5 gpio4_io19 input keeper dram_addr00 g1 nvcc_dram ddr alt0 dram_addr00 output 100 k ? pull-up dram_addr01 g2 nvcc_dram ddr alt0 dram_addr01 output 100 k ? pull-up dram_addr02 h1 nvcc_dram ddr alt0 dram_addr02 output 100 k ? pull-up dram_addr03 j2 nvcc_dram ddr alt0 dram_addr03 output 100 k ? pull-up dram_addr04 m4 nvcc_dram ddr alt0 dram_addr04 output 100 k ? pull-up dram_addr05 h2 nvcc_dram ddr alt0 dram_addr05 output 100 k ? pull-up dram_addr06 e4 nvcc_dram ddr alt0 dram_addr06 output 100 k ? pull-up i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 128 nxp semiconductors package information and contact assignments dram_addr07 j4 nvcc_dram ddr alt0 dram_addr07 output 100 k ? pull-up dram_addr08 j5 nvcc_dram ddr alt0 dram_addr08 output 100 k ? pull-up dram_addr09 j1 nvcc_dram ddr alt0 dram_addr09 output 100 k ? pull-up dram_addr10 m2 nvcc_dram ddr alt0 dram_addr10 output 100 k ? pull-up dram_addr11 k5 nvcc_dram ddr alt0 dram_addr11 output 100 k ? pull-up dram_addr12 l3 nvcc_dram ddr alt0 dram_addr12 output 100 k ? pull-up dram_addr13 h4 nvcc_dram ddr alt0 dram_addr13 output 100 k ? pull-up dram_addr14 e3 nvcc_dram ddr alt0 dram_addr14 output 100 k ? pull-up dram_addr15 e2 nvcc_dram ddr alt0 dram_addr15 output 100 k ? pull-up dram_cas_b g4 nvcc_dram ddr alt0 dram_cas_b output 100 k ? pull-up dram_cs0_b l1 nvcc_dram ddr alt0 dram_cs0_b output 100 k ? pull-up dram_cs1_b h5 nvcc_dram ddr alt0 dram_cs1_b output 100 k ? pull-up dram_data00 t3 nvcc_dram ddr alt0 dram_data00 input 100 k ? pull-up dram_data01 n5 nvcc_dram ddr alt0 dram_data01 input 100 k ? pull-up dram_data02 t4 nvcc_dram ddr alt0 dram_data02 input 100 k ? pull-up dram_data03 t5 nvcc_dram ddr alt0 dram_data03 input 100 k ? pull-up dram_data04 u5 nvcc_dram ddr alt0 dram_data04 input 100 k ? pull-up dram_data05 t6 nvcc_dram ddr alt0 dram_data05 input 100 k ? pull-up dram_data06 r4 nvcc_dram ddr alt0 dram_data06 input 100 k ? pull-up dram_data07 u3 nvcc_dram ddr alt0 dram_data07 input 100 k ? pull-up dram_data08 p1 nvcc_dram ddr alt0 dram_data08 input 100 k ? pull-up table 94. 9 x 9 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 129 dram_data09 u2 nvcc_dram ddr alt0 dram_data09 input 100 k ? pull-up dram_data10 p3 nvcc_dram ddr alt0 dram_data10 input 100 k ? pull-up dram_data11 r2 nvcc_dram ddr alt0 dram_data11 input 100 k ? pull-up dram_data12 p4 nvcc_dram ddr alt0 dram_data12 input 100 k ? pull-up dram_data13 n2 nvcc_dram ddr alt0 dram_data13 input 100 k ? pull-up dram_data14 n1 nvcc_dram ddr alt0 dram_data14 input 100 k ? pull-up dram_data15 p2 nvcc_dram ddr alt0 dram_data15 input 100 k ? pull-up dram_dqm0 u4 nvcc_dram ddr alt0 dram_dqm0 output 100 k ? pull-up dram_dqm1 r1 nvcc_dram ddr alt0 dram_dqm1 output 100 k ? pull-up dram_odt0 k2 nvcc_dram ddr alt0 dram_odt0 output 100 k ? pull-down dram_odt1 e1 nvcc_dram ddr alt0 dram_odt1 output 100 k ? pull-down dram_ras_b l4 nvcc_dram ddr alt0 dram_ras_b output 100 k ? pull-up dram_reset f2 nvcc_dram ddr alt0 dram_reset output 100 k ? pull-down dram_sdba0 h3 nvcc_dram ddr alt0 dram_sdba0 output 100 k ? pull-up dram_sdba1 f5 nvcc_dram ddr alt0 dram_sdba1 output 100 k ? pull-up dram_sdba2 g3 nvcc_dram ddr alt0 dram_sdba2 output 100 k ? pull-up dram_sdcke0 l2 nvcc_dram ddr alt0 dram_sdcke0 output 100 k ? pull-down dram_sdcke1 k1 nvcc_dram ddr alt0 dram_sdcke1 output 100 k ? pull-down dram_sdclk0_n k4 nvcc_dram ddrc lk alt0 dram_sdclk0_n input 100 k ? pull-up dram_sdclk0_p k3 nvcc_dram ddrc lk alt0 dram_sdclk0_p input 100 k ? pull-up dram_sdqs0_n r5 nvcc_dram ddrc lk alt0 dram_sdqs0_n input 100 k ? pull-down table 94. 9 x 9 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 130 nxp semiconductors package information and contact assignments dram_sdqs0_p p5 nvcc_dram ddrc lk alt0 dram_sdqs0_p input 100 k ? pull-down dram_sdqs1_n n4 nvcc_dram ddrc lk alt0 dram_sdqs1_p input 100 k ? pull-down dram_sdqs1_p n3 nvcc_dram ddrc lk alt0 dram_sdqs1_n input 100 k ? pull-down dram_sdwe_b f4 nvcc_dram ddr alt0 dram_sdwe_b output 100 k ? pull-up dram_zqpad t2 nvcc_dram gpio ? dram_zqpad input keeper enet1_rx_data0 g17 nvcc_enet gpio alt5 gpio2_io0 input keeper enet1_rx_data1 f16 nvcc_enet gpio alt5 gpio2_io1 input keeper enet1_rx_en g16 nvcc_enet gpio alt5 gpio2_io2 input keeper enet1_rx_er g14 nvcc_enet gpio alt5 gpio2_io7 input keeper enet1_tx_clk g15 nvcc_enet gpio alt5 gpio2_io6 input keeper enet1_tx_data0 e16 nvcc_enet gpio alt5 gpio2_io3 input keeper enet1_tx_data1 f13 nvcc_enet gpio alt5 gpio2_io4 input keeper enet1_tx_en f15 nvcc_enet gpio alt5 gpio2_io5 input keeper enet2_rx_data0 e17 nvcc_enet gpio alt5 gpio2_io8 input keeper enet2_rx_data1 d17 nvcc_enet gpio alt5 gpio2_io9 input keeper enet2_rx_en d16 nvcc_enet gpio alt5 gpio2_io10 input keeper enet2_rx_er h13 nvcc_enet gpio alt5 gpio2_io15 input keeper enet2_tx_clk h14 nvcc_enet gpio alt5 gpio2_io14 input keeper enet2_tx_data0 e14 nvcc_enet gpio alt5 gpio2_io11 input keeper enet2_tx_data1 f14 nvcc_enet gpio alt5 gpio2_io12 input keeper enet2_tx_en e15 nvcc_enet gpio alt5 gpio2_io13 input keeper gpio1_io00 m14 nvcc_gpio gpio alt5 gpio1_io00 input keeper gpio1_io01 m15 nvcc_gpio gpio alt5 gpio1_io01 input keeper gpio1_io02 m16 nvcc_gpio gpio alt5 gpio1_io02 input keeper gpio1_io03 n16 nvcc_gpio gpio alt5 gpio1_io03 input keeper gpio1_io04 n17 nvcc_gpio gpio alt5 gpio1_io04 input keeper gpio1_io05 p15 nvcc_gpio gpio alt5 gpio1_io05 input keeper gpio1_io06 n15 nvcc_gpio gpio alt5 gpio1_io06 input keeper gpio1_io07 n14 nvcc_gpio gpio alt5 gpio1_io07 input keeper gpio1_io08 p14 nvcc_gpio gpio alt5 gpio1_io08 input keeper gpio1_io09 p16 nvcc_gpio gpio alt5 gpio1_io09 input keeper table 94. 9 x 9 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 131 jtag_mod r13 nvcc_gpio sjc alt0 sjc_mod input 100 k ? pull-up jtag_tck r17 nvcc_gpio sjc alt0 sjc_tck input 47 k ? pull-up jtag_tdi p17 nvcc_gpio sjc alt0 sjc_tdi input 47 k ? pull-up jtag_tdo r16 nvcc_gpio sjc alt0 sjc_tdo output keeper jtag_tms r14 nvcc_gpio sjc alt0 sjc_tms input 47 k ? pull-up jtag_trst_b p13 nvcc_gpio sjc alt0 sjc_trstb input 47 k ? pull-up lcd_clk c11 nvcc_lcd gpio alt5 gpio3_io0 input keeper lcd_data00 d11 nvcc_lcd gpio alt5 gpio3_io5 input keeper lcd_data01 b12 nvcc_lcd gpio alt5 gpio3_io6 input keeper lcd_data02 d10 nvcc_lcd gpio alt5 gpio3_io7 input keeper lcd_data03 b11 nvcc_lcd gpio alt5 gpio3_io8 input keeper lcd_data04 a11 nvcc_lcd gpio alt5 gpio3_io9 input keeper lcd_data05 d12 nvcc_lcd gpio alt5 gpio3_io10 input keeper lcd_data06 d13 nvcc_lcd gpio alt5 gpio3_io11 input keeper lcd_data07 c12 nvcc_lcd gpio alt5 gpio3_io12 input keeper lcd_data08 b13 nvcc_lcd gpio alt5 gpio3_io13 input keeper lcd_data09 a13 nvcc_lcd gpio alt5 gpio3_io14 input keeper lcd_data10 d14 nvcc_lcd gpio alt5 gpio3_io15 input keeper lcd_data11 c13 nvcc_lcd gpio alt5 gpio3_io16 input keeper lcd_data12 c14 nvcc_lcd gpio alt5 gpio3_io17 input keeper lcd_data13 a14 nvcc_lcd gpio alt5 gpio3_io18 input keeper lcd_data14 b14 nvcc_lcd gpio alt5 gpio3_io19 input keeper lcd_data15 a16 nvcc_lcd gpio alt5 gpio3_io20 input keeper lcd_data16 a15 nvcc_lcd gpio alt5 gpio3_io21 input keeper lcd_data17 d15 nvcc_lcd gpio alt5 gpio3_io22 input keeper lcd_data18 b15 nvcc_lcd gpio alt5 gpio3_io23 input keeper lcd_data19 e12 nvcc_lcd gpio alt5 gpio3_io24 input keeper lcd_data20 b17 nvcc_lcd gpio alt5 gpio3_io25 input keeper lcd_data21 c16 nvcc_lcd gpio alt5 gpio3_io26 input keeper lcd_data22 b16 nvcc_lcd gpio alt5 gpio3_io27 input keeper lcd_data23 c17 nvcc_lcd gpio alt5 gpio3_io28 input keeper table 94. 9 x 9 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 132 nxp semiconductors package information and contact assignments lcd_enable a10 nvcc_lcd gpio alt5 gpio3_io1 input keeper lcd_hsync b10 nvcc_lcd gpio alt5 gpio3_io2 input keeper lcd_reset e10 nvcc_lcd gpio alt5 gpio3_io4 input keeper lcd_vsync c10 nvcc_lcd gpio alt5 gpio3_io3 input keeper nand_ale d8 nvcc_nand gpio alt5 gpio4_io10 input keeper nand_ce0_b e8 nvcc_nand gpio alt5 gpio4_io13 input keeper nand_ce1_b b6 nvcc_nand gpio alt5 gpio4_io14 input keeper nand_cle b7 nvcc_nand gpio alt5 gpio4_io15 input keeper nand_data00 d7 nvcc_nand gpio alt5 gpio4_io2 input keeper nand_data01 a9 nvcc_nand gpio alt5 gpio4_io3 input keeper nand_data02 c9 nvcc_nand gpio alt5 gpio4_io4 input keeper nand_data03 c7 nvcc_nand gpio alt5 gpio4_io5 input keeper nand_data04 c8 nvcc_nand gpio alt5 gpio4_io6 input keeper nand_data05 a6 nvcc_nand gpio alt5 gpio4_io7 input keeper nand_data06 b9 nvcc_nand gpio alt5 gpio4_io8 input keeper nand_data07 b8 nvcc_nand gpio alt5 gpio4_io9 input keeper nand_dqs e6 nvcc_nand gpio alt5 gpio4_io16 input keeper nand_re_b d9 nvcc_nand gpio alt5 gpio4_io0 input keeper nand_ready_b e9 nvcc_nand gpio alt5 gpio4_io12 input keeper nand_we_b a8 nvcc_nand gpio alt5 gpio4_io1 input keeper nand_wp_b d6 nvcc_nand gpio alt5 gpio4_io11 input keeper onoff r6 vdd_snvs_in src a lt0 src_reset_b input 100 k ? pull-up por_b r10 vdd_snvs_in src alt0 src_por_b input 100 k ? pull-up rtc_xtali t12 vdd_snvs_ca p anal og ?rtc_xtali ?? rtc_xtalo u12 vdd_snvs_ca p anal og ?rtc_xtalo ?? sd1_clk c5 nvcc_sd gpio alt5 gpio2_io17 input keeper sd1_cmd c6 nvcc_sd gpio alt5 gpio2_io16 input keeper sd1_data0 a5 nvcc_sd gpio alt5 gpio2_io18 input keeper sd1_data1 a4 nvcc_sd gpio alt5 gpio2_io19 input keeper sd1_data2 b5 nvcc_sd gpio alt5 gpio2_io20 input keeper sd1_data3 b4 nvcc_sd gpio alt5 gpio2_io21 input keeper table 94. 9 x 9 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 133 snvs_pmic_on_req t7 vdd_snvs_in gpio alt0 snvs_pmic_on_req output 100 k ? pull-up snvs_tamper0 r8 vdd_snvs_in gpio alt5 gpio5_io00/snvs_tampe r0 1 input keeper 1, 2 snvs_tamper1 p6 vdd_snvs_in gpio alt5 gpio5_io01/snvs_tampe r1 1 input keeper/n ot connecte d 1,2 snvs_tamper2 n10 vdd_snvs_in gpio alt5 gpio5_io02/snvs_tampe r2 1 input keeper/n ot connecte d 1,2 snvs_tamper3 p10 vdd_snvs_in gpio alt5 gpio5_io03/snvs_tampe r3 1 input keeper/n ot connecte d 1,2 snvs_tamper4 p7 vdd_snvs_in gpio alt5 gpio5_io04/snvs_tampe r4 1 input keeper/n ot connecte d 1,2 snvs_tamper5 p8 vdd_snvs_in gpio alt5 gpio5_io05/snvs_tampe r5 1 input keeper/n ot connecte d 1,2 snvs_tamper6 r7 vdd_snvs_in gpio alt5 gpio5_io06/snvs_tampe r6 1 input keeper/n ot connecte d 1,2 snvs_tamper7 n9 vdd_snvs_in gpio alt5 gpio5_io07/snvs_tampe r7 1 input keeper/n ot connecte d 1,2 snvs_tamper8 n8 vdd_snvs_in gpio alt5 gpio5_io08/snvs_tampe r8 1 input keeper/n ot connecte d 1,2 snvs_tamper9 p9 vdd_snvs_in gpio alt5 gpio5_io09/snvs_tampe r9 1 input keeper/n ot connecte d 1,2 test_mode n7 vdd_snvs_in tcu alt0 tcu_test_mode input keeper uart1_cts_b l14 nvcc_uart gpio alt5 gpio1_io18 input keeper uart1_rts_b k14 nvcc_uart gpio alt5 gpio1_io19 input keeper uart1_rx_data l17 nvcc_uart gpio alt5 gpio1_io17 input keeper uart1_tx_data l15 nvcc_uart gpio alt5 gpio1_io16 input keeper table 94. 9 x 9 mm functional contact assignments (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 134 nxp semiconductors package information and contact assignments uart2_cts_b j17 nvcc_uart gpio alt5 gpio1_io22 input keeper uart2_rts_b j14 nvcc_uart gpio alt5 gpio1_io23 input keeper uart2_rx_data k16 nvcc_uart gpio alt5 gpio1_io21 input keeper uart2_tx_data l16 nvcc_uart gpio alt5 gpio1_io20 input keeper uart3_cts_b h16 nvcc_uart gpio alt5 gpio1_io26 input keeper uart3_rts_b h15 nvcc_uart gpio alt5 gpio1_io27 input keeper uart3_rx_data k15 nvcc_uart gpio alt5 gpio1_io25 input keeper uart3_tx_data k17 nvcc_uart gpio alt5 gpio1_io24 input keeper uart4_rx_data h17 nvcc_uart gpio alt5 gpio1_io29 input keeper uart4_tx_data j16 nvcc_uart gpio alt5 gpio1_io28 input keeper uart5_rx_data j13 nvcc_uart gpio alt5 gpio1_io31 input keeper uart5_tx_data k13 nvcc_uart gpio alt5 gpio1_io30 input keeper usb_otg1_chd_b t15 open drain gpio ? usb_otg1_chd_b ? ? usb_otg1_dn r11 vdd_usb_cap anal og ? usb_otg1_dn ? ? usb_otg1_dp p11 vdd_usb_cap anal og ? usb_otg1_dp ? ? usb_otg1_vbus t9 usb_vbus vbus powe r ? usb_otg1_vbus ? ? usb_otg2_dn t10 vdd_usb_cap anal og ? usb_otg2_dn ? ? usb_otg2_dp u10 vdd_usb_cap anal og ? usb_otg2_dp ? ? usb_otg2_vbus u9 usb_vbus vbus powe r ? usb_otg2_vbus ? ? xtali t14 nvcc_pll anal og ?xtali ?? xtalo u14 nvcc_pll anal og ?xtalo ?? 1 snvs_tamper0 to snvs_tamper9 can be configured as gpio or tamper detection pin, it is depending on the fuse setting tamper_pin_disable[1:0]. when the pad is configur ed as gpio, the value is keeper out of reset. 2 snvs_tamper0 to snvs_tamper9 is input unconnected in the following conditions. ?snvs low power mode when configured as gpio ?tamper functions are not used when configured as tamper detection pins it is required to connect external 1m ohm pull-up or pull-down resistors to the pad to avoid the undesired leakage under two conditions above. table 94. 9 x 9 mm functional contact assignments (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 135 6.2.3 9 x 9 mm, 0.5 mm pitch, ball map table 95 shows the 9 x 9 mm, 0.5 mm pitch ball map for the i.mx 6ull. table 95. 9x9 mm, 0.5 mm pitch, ball map 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a vss csi_data06 sd1_data1 sd1_data0 nand_data05 vss nand_web nand_data01 lcd_enable lcd_data04 vss lcd_data09 lcd_data13 lcd_data16 lcd_data15 vss a b vss csi_data02 csi_data05 sd1_data3 sd1_data2 nand_ce1_b nand_cle nand_data07 nand_data06 lcd_hsync lcd_data03 lcd_data01 lcd_data08 lcd_data14 lcd_data18 lcd_data22 lcd_data20 b c csi_mclk csi_data07 csi_data00 csi_data04 sd1_clk sd1_cmd nand_data03 nand_data04 nand_data02 lcd_vsync lcd_clk lcd_data07 lcd_data11 lcd_data12 vss lcd_data21 lcd_data23 c d csi_data03 csi_hsync csi_vsync csi_data01 csi_pixclk nand_wp_b nand_data00 nand_ale nand_re_b lcd_data02 lcd_data00 lcd_data05 lcd_data06 lcd_data10 lcd_data17 enet2_rx_en enet2_rx_data1 d e dram_odt1 dram_addr15 dram_addr14 dram_addr06 nvcc_csi nand_dqs nvcc_sd1 nand_ce0_b nand_ready_b lcd_reset nvcc_nand lcd_data19 nvcc_lcd enet2_tx_data0 enet2_tx_en enet1_tx_data0 enet2_rx_data0 e f vss dram_reset vss dram_sdwe_b dram_sdba1 vss vss enet1_tx_data1 enet2_tx_data1 enet1_tx_en enet1_rx_data1 vss f g dram_addr00 dram_addr01 dram_sdba2 dram_cas_b nvcc_dram vdd_soc_cap vdd_soc_cap vdd_arm_cap vdd_arm_cap vdd_arm_cap nvcc_enet enet1_rx_er enet1_tx_clk enet1_rx_en enet1_rx_data0 g i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 136 nxp semiconductors package information and contact assignments h dram_addr02 dram_addr05 dram_sdba0 dram_addr13 dram_csi_b vss vdd_soc_cap vdd_soc_cap vdd_arm_cap vdd_arm_cap vdd_arm_cap vss enet2_rx_er enet2_tx_clk uart3_rts_b uart3_cts_b uart4_rx_data h j dram_addr09 dram_addr03 vss dram_addr07 dram_addr08 vdd_soc_cap vdd_soc_cap vdd_soc_in vdd_soc_in vdd_soc_in uart5_rx_data uart2_rts_b vss uart4_tx_data uart2_cts_b j k dram_sdcke1 dram_odt0 dram_sdclk0_p dram_sdclk0_n dram_addr11 nvcc_dram_2p5 vdd_soc_cap vdd_soc_cap vdd_soc_in vdd_soc_in vdd_soc_in vss uart5_tx_data uart1_rts_b uart3_rx_data uart2_rx_data uart3_tx_data k l dram_cs0_b dram_sdcke0 dram_addr12 dram_ras_b nvcc_dram vdd_soc_cap vdd_soc_cap vdd_soc_in vdd_soc_in vdd_soc_in nvcc_uart uart1_cts_b uart1_tx_data uart2_tx-data uart1_rx_data l m vss dram_addr10 vss dram_addr04 nvcc_dram vss ngnd_kel0 nvcc_gpio gpio1_io00 gpio_io01 gpio1_io02 vss m n dram_data14 dram_data13 dram_sdqs1_p dram_sdqs1_n dram_data01 nvcc_dram test_mode snvs_tamper8 snvs_tamper7 snvs_damper2 vdd_usb_cap vdd_snvs_cap adc_vrefh gpio1_io07 gpio1_io06 gpio1_io03 gpio1_io04 n p dram_data08 dram_data15 dram_data10 dram_data12 dram_sdqs0_p snvs_tamper1 snvs_tamper4 snvs_tamper5 snvs_tamper9 snvs_tamper3 usb_otg1_dp vdd_snvs_in jtag_trst_b gpio1_io08 gpio1_io05 gpio1_io09 jtag_tdi p table 95. 9x9 mm, 0.5 mm pitch, ball map (continued) package information and contact assignments i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 nxp semiconductors 137 r dram_dm1 dram_data11 vss dram_data06 dram_sdqs0_n onoff snvs_tamper6 snvs_tamper0 vss por_b usb_otg1_dn vss jtag_mod jtag_tms vss jtag_tdo jtag_tck r t dram_vref dram_zqpad dram_data00 dram_data02 dram_data03 dram_data05 snvs_pmic_on_req boot_mode0 usb_otg1_vbus usb_otg2_dn gpanaio rtc_xtali nvcc_pll xtali usb_otg1_chd_b ccm_clk1_p vdda_adc_3p3 t u vss dram_data09 dram_data07 dram_dqm0 dram_data04 vss ccm_pmic_stby_req boot_mode1 usb_otg2_vbus usb_otg2_dp vdd_high_cap rtc_xtalo vss xtalo vdd_high_in ccm_clk1_n vss u 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 table 95. 9x9 mm, 0.5 mm pitch, ball map (continued) i.mx 6ull applications processors for in dustrial products, rev. 1.2, 11/2017 138 nxp semiconductors revision history 7 revision history table 96 provides a revision history for this data sheet. table 96. i.mx 6ull data sheet document revision history rev. number date substantive change(s) 1.2 11/2017 ? updated the part numbers and added a ne w part number (mcimx6y2cvk08ab) in the ta bl e 1 , "ordering information" ? updated the silicon revision number in the figure 1, "part number nomenclature?i.mx 6ull" ? updated the gpio1_io09 signal name in the table 85, "sd/mmc boot through usdhc1" and added a footnote ? updated the nand_ale signal name in the table 86, "sd/mmc boot through usdhc2" and added a footnote 1.1 05/2017 ? changed terminology from ?floating? to ?not connected? ? changed the lv-ddr3 to ddr3l in the section 1.2, ?features " ? added a footnote regarding maximum voltage allowance in the table 7, "absolute maximum ratings" ? updated the minimum value of vdd_soc_cap in the low power run mode: ldo enabled from the table 10, "operating ranges" ? removed the lpsr mode in the section 4.1.6, ?power modes " ? removed a note in the section 4.2.1, ?power-up sequence " ? replaced the mmdc compatible information with a cross reference in the section 4.6.3, ?ddr i/o dc parameters " and section 4.7.2, ?ddr i/o ac parameters " ? removed the section 4.9.4, ?ddr sdram specific parameters (ddr3 and lpddr2)? ? added a new section 4.10, ?multi-mode ddr controller (mmdc) " ? changed sd3 min to 1.7 ns in the table 51, "emmc4.4/4.41 interface timing specification" 1 02/2017 ? added a new part number in the table 1, "ordering information" ? updated the part differentiator number 3 to reserved, removed 300 mhz from frequency, and added 792 mhz in the figure 1, "part number nomenclature?i.mx 6ull" ? updated the ddr i/o supply voltage and added a table not in the table 7, "absolute maximum ratings" ? updated table 10, "operating ranges" ? added max. current for vdd_soc_in at 792 mhz in the table 13, "maximum supply currents" ? updated the ldo_2p5 of the low power idle: ldo bypassed row in the ta b l e 1 5 , " l o w po w e r mode current and power consumption" and the vdd_soc_in supply voltage for ldo enable mode ? updated the figure 18, "asynchronous a/d muxed write access" ? added a new section 4.12.9.1, ?lcdif signal mapping " ? added a note in the section 4.2.1, ?power-up sequence " ? updated vdd_high_cap pin assignment in the table 90, "14x14 mm supp lies contact assignment" ? updated vdd_high_cap pin in the table 92, "14 x 14 mm, 0.8 mm pitch, ball map" 0 09/2016 ? initial public release document number: IMX6ULLIEC rev. 1.2 11/2017 information in this document is provid ed solely to enable system and software implementers to use nxp products. there ar e no express or implied copyright licenses granted hereunder to design or fabricat e any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any produc t or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer? customer?s technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions. nxp, the nxp logo, freescale, the freescale logo, and the energy efficient solutions logo are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm and cortex are trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ? 2016-2017 nxp b.v. how to reach us: home page: nxp.com web support: nxp.com/support |
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